arm64: dts: qcom: Add display support for QCS615

Add display MDSS and DSI configuration for QCS615 platform.
QCS615 has a DP port, and DP support will be added in a later patch.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Li Liu <li.liu@oss.qualcomm.com>
Signed-off-by: Fange Zhang <fange.zhang@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250903-add-display-support-for-qcs615-platform-v8-1-7971c05d1262@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index eb6f69be4a82ea47486f5c8e39519d0952b146cb..d1dbfa3bd81c3d999bd79fc92ad85312c2f83087 100644 (file)
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -3,6 +3,7 @@
  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
 #include <dt-bindings/clock/qcom,qcs615-camcc.h>
 #include <dt-bindings/clock/qcom,qcs615-dispcc.h>
 #include <dt-bindings/clock/qcom,qcs615-gcc.h>
@@ -3795,14 +3796,191 @@
                        #power-domain-cells = <1>;
                };
 
+               mdss: display-subsystem@ae00000 {
+                       compatible = "qcom,sm6150-mdss";
+                       reg = <0x0 0x0ae00000 0x0 0x1000>;
+                       reg-names = "mdss";
+
+                       interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                                       <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       interconnect-names = "mdp0-mem",
+                                            "cpu-cfg";
+
+                       power-domains = <&dispcc MDSS_CORE_GDSC>;
+
+                       clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                <&gcc GCC_DISP_HF_AXI_CLK>,
+                                <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+
+                       iommus = <&apps_smmu 0x800 0x0>;
+
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       status = "disabled";
+
+                       mdss_mdp: display-controller@ae01000 {
+                               compatible = "qcom,sm6150-dpu";
+                               reg = <0x0 0x0ae01000 0x0 0x8f000>,
+                                     <0x0 0x0aeb0000 0x0 0x2008>;
+                               reg-names = "mdp",
+                                           "vbif";
+
+                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                        <&gcc GCC_DISP_HF_AXI_CLK>,
+                                        <&dispcc DISP_CC_MDSS_MDP_CLK>,
+                                        <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+                               clock-names = "iface",
+                                             "bus",
+                                             "core",
+                                             "vsync";
+
+                               operating-points-v2 = <&mdp_opp_table>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
+
+                               interrupts-extended = <&mdss 0>;
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               dpu_intf0_out: endpoint {
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               dpu_intf1_out: endpoint {
+                                                       remote-endpoint = <&mdss_dsi0_in>;
+                                               };
+                                       };
+                               };
+
+                               mdp_opp_table: opp-table {
+                                       compatible = "operating-points-v2";
+
+                                       opp-192000000 {
+                                               opp-hz = /bits/ 64 <192000000>;
+                                               required-opps = <&rpmhpd_opp_low_svs>;
+                                       };
+
+                                       opp-256000000 {
+                                               opp-hz = /bits/ 64 <256000000>;
+                                               required-opps = <&rpmhpd_opp_svs>;
+                                       };
+
+                                       opp-307200000 {
+                                               opp-hz = /bits/ 64 <307200000>;
+                                               required-opps = <&rpmhpd_opp_nom>;
+                                       };
+                               };
+                       };
+
+                       mdss_dsi0: dsi@ae94000 {
+                               compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+                               reg = <0x0 0x0ae94000 0x0 0x400>;
+                               reg-names = "dsi_ctrl";
+
+                               interrupts-extended = <&mdss 4>;
+
+                               clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+                                        <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+                                        <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+                                        <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+                                        <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                        <&gcc GCC_DISP_HF_AXI_CLK>;
+                               clock-names = "byte",
+                                             "byte_intf",
+                                             "pixel",
+                                             "core",
+                                             "iface",
+                                             "bus";
+
+                               assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+                                                 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+                               assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+                                                        <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
+
+                               operating-points-v2 = <&dsi0_opp_table>;
+                               power-domains = <&rpmhpd RPMHPD_CX>;
+
+                               phys = <&mdss_dsi0_phy>;
+
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               status = "disabled";
+
+                               dsi0_opp_table: opp-table {
+                                       compatible = "operating-points-v2";
+
+                                       opp-164000000 {
+                                               opp-hz = /bits/ 64 <164000000>;
+                                               required-opps = <&rpmhpd_opp_low_svs>;
+                                       };
+                               };
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               mdss_dsi0_in: endpoint {
+                                                       remote-endpoint = <&dpu_intf1_out>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               mdss_dsi0_out: endpoint {
+                                               };
+                                       };
+                               };
+                       };
+
+                       mdss_dsi0_phy: phy@ae94400 {
+                               compatible = "qcom,sm6150-dsi-phy-14nm";
+                               reg = <0x0 0x0ae94400 0x0 0x100>,
+                                     <0x0 0x0ae94500 0x0 0x300>,
+                                     <0x0 0x0ae94800 0x0 0x124>;
+                               reg-names = "dsi_phy",
+                                           "dsi_phy_lane",
+                                           "dsi_pll";
+
+                               #clock-cells = <1>;
+                               #phy-cells = <0>;
+
+                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                        <&rpmhcc RPMH_CXO_CLK>;
+                               clock-names = "iface",
+                                             "ref";
+
+                               status = "disabled";
+                       };
+               };
+
                dispcc: clock-controller@af00000 {
                        compatible = "qcom,qcs615-dispcc";
                        reg = <0 0x0af00000 0 0x20000>;
 
                        clocks = <&rpmhcc RPMH_CXO_CLK>,
                                 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
-                                <0>,
-                                <0>,
+                                <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+                                <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
                                 <0>,
                                 <0>,
                                 <0>;