clk: renesas: r9a09g056-cpg: Add clock and reset entries for GBETH0/1

Add clock and reset entries for GBETH instances. Include core clocks for
PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks
used as clock sources for the GBETH IP.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250513154635.273664-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
index e2712a25c43a39f92aa08d13b150c8ad7fe22ac5..5582041455c51a0d8a746d0466f9a2d72ba01348 100644 (file)
--- a/drivers/clk/renesas/r9a09g056-cpg.c
+++ b/drivers/clk/renesas/r9a09g056-cpg.c
@@ -28,6 +28,7 @@ enum clk_ids {
        CLK_PLLCLN,
        CLK_PLLDTY,
        CLK_PLLCA55,
+       CLK_PLLETH,
 
        /* Internal Core Clocks */
        CLK_PLLCM33_DIV16,
@@ -35,6 +36,15 @@ enum clk_ids {
        CLK_PLLCLN_DIV8,
        CLK_PLLDTY_ACPU,
        CLK_PLLDTY_ACPU_DIV4,
+       CLK_PLLDTY_DIV8,
+       CLK_PLLETH_DIV_250_FIX,
+       CLK_PLLETH_DIV_125_FIX,
+       CLK_CSDIV_PLLETH_GBE0,
+       CLK_CSDIV_PLLETH_GBE1,
+       CLK_SMUX2_GBE0_TXCLK,
+       CLK_SMUX2_GBE0_RXCLK,
+       CLK_SMUX2_GBE1_TXCLK,
+       CLK_SMUX2_GBE1_RXCLK,
 
        /* Module Clocks */
        MOD_CLK_BASE,
@@ -57,6 +67,19 @@ static const struct clk_div_table dtable_2_64[] = {
        {0, 0},
 };
 
+static const struct clk_div_table dtable_2_100[] = {
+       {0, 2},
+       {1, 10},
+       {2, 100},
+       {0, 0},
+};
+
+/* Mux clock tables */
+static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
+static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
+static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
+static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" };
+
 static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
@@ -68,6 +91,7 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
        DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
        DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
        DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
+       DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
 
        /* Internal Core Clocks */
        DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
@@ -77,6 +101,18 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
 
        DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
        DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
+       DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
+
+       DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
+       DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
+       DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0,
+                 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100),
+       DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1,
+                 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100),
+       DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk),
+       DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
+       DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
+       DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
 
        /* Core Clocks */
        DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
@@ -89,6 +125,10 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
        DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55,
                 CDDIV1_DIVCTL3, dtable_1_8),
        DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
+       DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G056_GBETH_0_CLK_PTP_REF_I,
+                 CLK_PLLETH_DIV_125_FIX, 1, 1),
+       DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G056_GBETH_1_CLK_PTP_REF_I,
+                 CLK_PLLETH_DIV_125_FIX, 1, 1),
 };
 
 static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
@@ -120,6 +160,30 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
                                                BUS_MSTOP(8, BIT(4))),
        DEF_MOD("sdhi_2_aclk",                  CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
                                                BUS_MSTOP(8, BIT(4))),
+       DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
+                                               BUS_MSTOP(8, BIT(5)), 1),
+       DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
+                                               BUS_MSTOP(8, BIT(5)), 1),
+       DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
+                                               BUS_MSTOP(8, BIT(5)), 1),
+       DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
+                                               BUS_MSTOP(8, BIT(5)), 1),
+       DEF_MOD("gbeth_0_aclk_csr_i",           CLK_PLLDTY_DIV8, 11, 12, 5, 28,
+                                               BUS_MSTOP(8, BIT(5))),
+       DEF_MOD("gbeth_0_aclk_i",               CLK_PLLDTY_DIV8, 11, 13, 5, 29,
+                                               BUS_MSTOP(8, BIT(5))),
+       DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
+                                               BUS_MSTOP(8, BIT(6)), 1),
+       DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
+                                               BUS_MSTOP(8, BIT(6)), 1),
+       DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0,
+                                               BUS_MSTOP(8, BIT(6)), 1),
+       DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1,
+                                               BUS_MSTOP(8, BIT(6)), 1),
+       DEF_MOD("gbeth_1_aclk_csr_i",           CLK_PLLDTY_DIV8, 12, 2, 6, 2,
+                                               BUS_MSTOP(8, BIT(6))),
+       DEF_MOD("gbeth_1_aclk_i",               CLK_PLLDTY_DIV8, 12, 3, 6, 3,
+                                               BUS_MSTOP(8, BIT(6))),
 };
 
 static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
@@ -130,6 +194,8 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
        DEF_RST(10, 7, 4, 24),          /* SDHI_0_IXRST */
        DEF_RST(10, 8, 4, 25),          /* SDHI_1_IXRST */
        DEF_RST(10, 9, 4, 26),          /* SDHI_2_IXRST */
+       DEF_RST(11, 0, 5, 1),           /* GBETH_0_ARESETN_I */
+       DEF_RST(11, 1, 5, 2),           /* GBETH_1_ARESETN_I */
 };
 
 const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {