arm64: dts: imx943-evk: add ENETC, EMDIO and PTP Timer support

Add ENETC instance 1~3, EMDIO and PTP Timer 0~1 support.
The EMDIO provides MDIO bus for ENETCs to access their external PHYs.
The PTP Timer provides current time with nanosecond resolution, precise
periodic pulse, pulse on timeout, and time capture on external pulse
support. It also provides PTP clock for ENETCs to implement time
synchronization as required for IEEE 1588 and  IEEE 802.1AS-2020.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
index c8c3eff9df1a23c52e74bf2bc5d4ba543bb5a65b..8b348f2941faa935cb950e1a532a85ab641924ba 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
@@ -12,6 +12,9 @@
        model = "NXP i.MX943 EVK board";
 
        aliases {
+               ethernet0 = &enetc3;
+               ethernet1 = &enetc1;
+               ethernet2 = &enetc2;
                i2c2 = &lpi2c3;
                i2c3 = &lpi2c4;
                i2c5 = &lpi2c6;
@@ -127,6 +130,30 @@
        };
 };
 
+&enetc1 {
+       clocks = <&scmi_clk IMX94_CLK_MAC4>;
+       clock-names = "ref";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_eth3>;
+       phy-handle = <&ethphy3>;
+       phy-mode = "rgmii-id";
+       status = "okay";
+};
+
+&enetc2 {
+       clocks = <&scmi_clk IMX94_CLK_MAC5>;
+       clock-names = "ref";
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_eth4>;
+       phy-handle = <&ethphy4>;
+       phy-mode = "rgmii-id";
+       status = "okay";
+};
+
+&enetc3 {
+       status = "okay";
+};
+
 &lpi2c3 {
        clock-frequency = <400000>;
        pinctrl-0 = <&pinctrl_lpi2c3>;
@@ -396,6 +423,39 @@
        status = "okay";
 };
 
+&netc_blk_ctrl {
+       assigned-clocks = <&scmi_clk IMX94_CLK_MAC4>,
+                         <&scmi_clk IMX94_CLK_MAC5>;
+       assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>,
+                                <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>;
+       assigned-clock-rates = <250000000>, <250000000>;
+       status = "okay";
+};
+
+&netc_emdio {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_emdio>;
+       status = "okay";
+
+       ethphy3: ethernet-phy@6 {
+               reg = <0x6>;
+               realtek,clkout-disable;
+       };
+
+       ethphy4: ethernet-phy@7 {
+               reg = <0x7>;
+               realtek,clkout-disable;
+       };
+};
+
+&netc_timer0 {
+       status = "okay";
+};
+
+&netc_timer1 {
+       status = "okay";
+};
+
 &sai1 {
        assigned-clocks = <&scmi_clk IMX94_CLK_AUDIOPLL1_VCO>,
                          <&scmi_clk IMX94_CLK_AUDIOPLL2_VCO>,
@@ -431,6 +491,46 @@
 };
 
 &scmi_iomuxc {
+       pinctrl_emdio: emdiogrp {
+               fsl,pins = <
+                       IMX94_PAD_ETH4_MDC_GPIO1__NETC_EMDC             0x57e
+                       IMX94_PAD_ETH4_MDIO_GPIO2__NETC_EMDIO           0x97e
+               >;
+       };
+
+       pinctrl_eth3: eth3grp {
+               fsl,pins = <
+                       IMX94_PAD_ETH3_TXD3__NETC_PINMUX_ETH3_TXD3              0x50e
+                       IMX94_PAD_ETH3_TXD2__NETC_PINMUX_ETH3_TXD2              0x50e
+                       IMX94_PAD_ETH3_TXD1__NETC_PINMUX_ETH3_TXD1              0x50e
+                       IMX94_PAD_ETH3_TXD0__NETC_PINMUX_ETH3_TXD0              0x50e
+                       IMX94_PAD_ETH3_TX_CTL__NETC_PINMUX_ETH3_TX_CTL          0x51e
+                       IMX94_PAD_ETH3_TX_CLK__NETC_PINMUX_ETH3_TX_CLK          0x59e
+                       IMX94_PAD_ETH3_RX_CTL__NETC_PINMUX_ETH3_RX_CTL          0x51e
+                       IMX94_PAD_ETH3_RX_CLK__NETC_PINMUX_ETH3_RX_CLK          0x59e
+                       IMX94_PAD_ETH3_RXD0__NETC_PINMUX_ETH3_RXD0              0x51e
+                       IMX94_PAD_ETH3_RXD1__NETC_PINMUX_ETH3_RXD1              0x51e
+                       IMX94_PAD_ETH3_RXD2__NETC_PINMUX_ETH3_RXD2              0x51e
+                       IMX94_PAD_ETH3_RXD3__NETC_PINMUX_ETH3_RXD3              0x51e
+               >;
+       };
+
+       pinctrl_eth4: eth4grp {
+               fsl,pins = <
+                       IMX94_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3              0x50e
+                       IMX94_PAD_ETH4_TXD2__NETC_PINMUX_ETH4_TXD2              0x50e
+                       IMX94_PAD_ETH4_TXD1__NETC_PINMUX_ETH4_TXD1              0x50e
+                       IMX94_PAD_ETH4_TXD0__NETC_PINMUX_ETH4_TXD0              0x50e
+                       IMX94_PAD_ETH4_TX_CTL__NETC_PINMUX_ETH4_TX_CTL          0x51e
+                       IMX94_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK          0x59e
+                       IMX94_PAD_ETH4_RX_CTL__NETC_PINMUX_ETH4_RX_CTL          0x51e
+                       IMX94_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK          0x59e
+                       IMX94_PAD_ETH4_RXD0__NETC_PINMUX_ETH4_RXD0              0x51e
+                       IMX94_PAD_ETH4_RXD1__NETC_PINMUX_ETH4_RXD1              0x51e
+                       IMX94_PAD_ETH4_RXD2__NETC_PINMUX_ETH4_RXD2              0x51e
+                       IMX94_PAD_ETH4_RXD3__NETC_PINMUX_ETH4_RXD3              0x51e
+               >;
+       };
 
        pinctrl_ioexpander_int2: ioexpanderint2grp {
                fsl,pins = <