**/
static s32 e1000_reset_hw_82540(struct e1000_hw *hw)
{
- u32 ctrl, icr, manc;
+ u32 ctrl, manc;
s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_reset_hw_82540");
E1000_WRITE_REG(hw, E1000_MANC, manc);
E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
- icr = E1000_READ_REG(hw, E1000_ICR);
+ E1000_READ_REG(hw, E1000_ICR);
return ret_val;
}
**/
static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
{
- u32 ledctl, ctrl, icr, manc;
+ u32 ledctl, ctrl, manc;
DEBUGFUNC("e1000_reset_hw_82541");
E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
/* Clear any pending interrupt events. */
- icr = E1000_READ_REG(hw, E1000_ICR);
+ E1000_READ_REG(hw, E1000_ICR);
return E1000_SUCCESS;
}
{
struct e1000_bus_info *bus = &hw->bus;
s32 ret_val = E1000_SUCCESS;
- u32 ctrl, icr;
+ u32 ctrl;
DEBUGFUNC("e1000_reset_hw_82542");
msec_delay(2);
E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
- icr = E1000_READ_REG(hw, E1000_ICR);
+ E1000_READ_REG(hw, E1000_ICR);
if (hw->revision_id == E1000_REVISION_2) {
if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
**/
static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
{
- u32 ctrl, icr;
+ u32 ctrl;
s32 ret_val = E1000_SUCCESS;
DEBUGFUNC("e1000_reset_hw_82543");
/* Masking off and clearing any pending interrupts */
E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
- icr = E1000_READ_REG(hw, E1000_ICR);
+ E1000_READ_REG(hw, E1000_ICR);
return ret_val;
}
struct e1000_adapter *adapter = netdev_priv ( netdev );
struct e1000_hw *hw = &adapter->hw;
uint32_t rctl;
- uint32_t icr;
DBG ( "e1000_close\n" );
- /* Acknowledge interrupts */
- icr = E1000_READ_REG ( hw, E1000_ICR );
-
+ /* Disable and acknowledge interrupts */
e1000_irq_disable ( adapter );
+ E1000_READ_REG ( hw, E1000_ICR );
/* disable receives */
rctl = E1000_READ_REG ( hw, E1000_RCTL );
**/
static s32 e1000e_reset_hw_80003es2lan(struct e1000_hw *hw)
{
- u32 ctrl, icr;
+ u32 ctrl;
s32 ret_val;
/*
/* Clear any pending interrupt events. */
ew32(IMC, 0xffffffff);
- icr = er32(ICR);
+ er32(ICR);
ret_val = e1000e_check_alt_mac_addr_generic(hw);
**/
static s32 e1000e_reset_hw_82571(struct e1000_hw *hw)
{
- u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
+ u32 ctrl, extcnf_ctrl, ctrl_ext;
s32 ret_val;
u16 i = 0;
/* Clear any pending interrupt events. */
ew32(IMC, 0xffffffff);
- icr = er32(ICR);
+ er32(ICR);
/* Install any alternate MAC address into RAR0 */
ret_val = e1000e_check_alt_mac_addr_generic(hw);
{
struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
u16 reg;
- u32 ctrl, icr, kab;
+ u32 ctrl, kab;
s32 ret_val;
/*
ew32(CRC_OFFSET, 0x65656565);
ew32(IMC, 0xffffffff);
- icr = er32(ICR);
+ er32(ICR);
kab = er32(KABGTXD);
kab |= E1000_KABGTXD_BGSQLBIAS;
struct e1000_adapter *adapter = netdev_priv ( netdev );
struct e1000_hw *hw = &adapter->hw;
uint32_t rctl;
- uint32_t icr;
DBGP ( "e1000_close\n" );
- /* Acknowledge interrupts */
- icr = E1000_READ_REG ( hw, E1000_ICR );
-
+ /* Disable and acknowledge interrupts */
e1000e_irq_disable ( adapter );
+ E1000_READ_REG ( hw, E1000_ICR );
/* disable receives */
rctl = E1000_READ_REG ( hw, E1000_RCTL );
**/
static s32 igb_reset_hw_82575(struct e1000_hw *hw)
{
- u32 ctrl, icr;
+ u32 ctrl;
s32 ret_val;
DEBUGFUNC("igb_reset_hw_82575");
/* Clear any pending interrupt events. */
E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
- icr = E1000_READ_REG(hw, E1000_ICR);
+ E1000_READ_REG(hw, E1000_ICR);
/* Install any alternate MAC address into RAR0 */
ret_val = igb_check_alt_mac_addr_generic(hw);
struct igb_adapter *adapter = netdev_priv ( netdev );
struct e1000_hw *hw = &adapter->hw;
uint32_t rctl;
- uint32_t icr;
DBGP ( "igb_close\n" );
- /* Acknowledge interrupts */
- icr = E1000_READ_REG ( hw, E1000_ICR );
-
+ /* Disable and acknowledge interrupts */
igb_irq_disable ( adapter );
+ E1000_READ_REG ( hw, E1000_ICR );
/* disable receives */
rctl = E1000_READ_REG ( hw, E1000_RCTL );
struct igbvf_adapter *adapter = netdev_priv ( netdev );
struct e1000_hw *hw = &adapter->hw;
uint32_t rxdctl;
- uint32_t icr;
DBG ( "igbvf_close\n" );
- icr = er32(EICR);
+ /* Disable and acknowledge interrupts */
igbvf_irq_disable ( adapter );
+ er32(EICR);
/* disable receives */
rxdctl = er32 ( RXDCTL(0) );