phy: phy-rockchip-samsung-hdptx: Swap the definitions of LCPLL_REF and ROPLL_REF

[ Upstream commit 2947c8065e9efdd3b6434d2817dc8896234a3fc0 ]

According to the datasheet, setting the dig_clk_sel bit of CMN_REG(0097)
to 1'b1 selects LCPLL as the reference clock, while setting it to 1'b0
selects the ROPLL.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250205105157.580060-2-damon.ding@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 2fb4f297fda3d64fc302b0f54b85838087433de9..920abf6fa9bdd8ac2f84ac3385d954585a9164aa 100644 (file)
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -94,8 +94,8 @@
 #define LCPLL_ALONE_MODE               BIT(1)
 /* CMN_REG(0097) */
 #define DIG_CLK_SEL                    BIT(1)
-#define ROPLL_REF                      BIT(1)
-#define LCPLL_REF                      0
+#define LCPLL_REF                      BIT(1)
+#define ROPLL_REF                      0
 /* CMN_REG(0099) */
 #define CMN_ROPLL_ALONE_MODE           BIT(2)
 #define ROPLL_ALONE_MODE               BIT(2)