phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions

[ Upstream commit e56272f2bb8314eb13b0eb0a4e8055831c700255 ]

Fix the following register definitions for REG_CSR_2L_RX{0,1}_REV0
registers:
- CSR_2L_PXP_VOS_PNINV
- CSR_2L_PXP_FE_GAIN_NORMAL_MODE
- CSR_2L_PXP_FE_GAIN_TRAIN_MODE

Fixes: d7d2818b9383 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/20240918-airoha-en7581-phy-fixes-v1-4-8291729a87f8@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/phy/phy-airoha-pcie-regs.h b/drivers/phy/phy-airoha-pcie-regs.h
index bb1f679ca1dfa09d2b2966c214517804005dcc48..b938a7b468fee3f65e4928ebcc1a5f7d2f85b762 100644 (file)
--- a/drivers/phy/phy-airoha-pcie-regs.h
+++ b/drivers/phy/phy-airoha-pcie-regs.h
@@ -197,9 +197,9 @@
 #define CSR_2L_PXP_TX1_MULTLANE_EN             BIT(0)
 
 #define REG_CSR_2L_RX0_REV0                    0x00fc
-#define CSR_2L_PXP_VOS_PNINV                   GENMASK(3, 2)
-#define CSR_2L_PXP_FE_GAIN_NORMAL_MODE         GENMASK(6, 4)
-#define CSR_2L_PXP_FE_GAIN_TRAIN_MODE          GENMASK(10, 8)
+#define CSR_2L_PXP_VOS_PNINV                   GENMASK(19, 18)
+#define CSR_2L_PXP_FE_GAIN_NORMAL_MODE         GENMASK(22, 20)
+#define CSR_2L_PXP_FE_GAIN_TRAIN_MODE          GENMASK(26, 24)
 
 #define REG_CSR_2L_RX0_PHYCK_DIV               0x0100
 #define CSR_2L_PXP_RX0_PHYCK_SEL               GENMASK(9, 8)