arm64: dts: qcom: sm8750: Add Iris VPU v3.5

Add Iris video codec to SM8750 SoC, which comes with significantly
different powering up sequence than previous SM8650, thus different
clocks and resets.  For consistency keep existing clock and clock-names
naming, so the list shares common part.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20260106-b4-sm8750-iris-dts-v4-1-97db1d1df3dd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 0a6f2a449c2048934e0bcdc4ad223c4459532c43..a76bf5193a70e876547714d7fbd64c3addb1538e 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,sm8750-gcc.h>
 #include <dt-bindings/clock/qcom,sm8750-tcsr.h>
+#include <dt-bindings/clock/qcom,sm8750-videocc.h>
 #include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
@@ -2811,6 +2812,126 @@
                        };
                };
 
+               iris: video-codec@aa00000 {
+                       compatible = "qcom,sm8750-iris";
+                       reg = <0x0 0x0aa00000 0x0 0xf0000>;
+
+                       clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+                                <&videocc VIDEO_CC_MVS0C_CLK>,
+                                <&videocc VIDEO_CC_MVS0_CLK>,
+                                <&gcc GCC_VIDEO_AXI1_CLK>,
+                                <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
+                                <&videocc VIDEO_CC_MVS0_FREERUN_CLK>;
+                       clock-names = "iface",
+                                     "core",
+                                     "vcodec0_core",
+                                     "iface1",
+                                     "core_freerun",
+                                     "vcodec0_core_freerun";
+
+                       dma-coherent;
+                       iommus = <&apps_smmu 0x1940 0>,
+                                <&apps_smmu 0x1947 0>;
+
+                       interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+                                       <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
+                                        &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+                       interconnect-names = "cpu-cfg",
+                                            "video-mem";
+
+                       interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+                       memory-region = <&video_mem>;
+
+                       operating-points-v2 = <&iris_opp_table>;
+
+                       power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+                                       <&videocc VIDEO_CC_MVS0_GDSC>,
+                                       <&rpmhpd RPMHPD_MXC>,
+                                       <&rpmhpd RPMHPD_MMCX>;
+                       power-domain-names = "venus",
+                                            "vcodec0",
+                                            "mxc",
+                                            "mmcx";
+
+                       resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+                                <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
+                                <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
+                                <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>;
+                       reset-names = "bus0",
+                                     "bus1",
+                                     "core",
+                                     "vcodec0_core";
+
+                       /*
+                        * IRIS firmware is signed by vendors, only
+                        * enable in boards where the proper signed firmware
+                        * is available.
+                        */
+                       status = "disabled";
+
+                       iris_opp_table: opp-table {
+                               compatible = "operating-points-v2";
+
+                               opp-240000000 {
+                                       opp-hz = /bits/ 64 <240000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs_d1>,
+                                                       <&rpmhpd_opp_low_svs_d1>;
+                               };
+
+                               opp-338000000 {
+                                       opp-hz = /bits/ 64 <338000000>;
+                                       required-opps = <&rpmhpd_opp_low_svs>,
+                                                       <&rpmhpd_opp_low_svs>;
+                               };
+
+                               opp-420000000 {
+                                       opp-hz = /bits/ 64 <420000000>;
+                                       required-opps = <&rpmhpd_opp_svs>,
+                                                       <&rpmhpd_opp_svs>;
+                               };
+
+                               opp-444000000 {
+                                       opp-hz = /bits/ 64 <444000000>;
+                                       required-opps = <&rpmhpd_opp_svs_l1>,
+                                                       <&rpmhpd_opp_svs_l1>;
+                               };
+
+                               opp-533333334 {
+                                       opp-hz = /bits/ 64 <533333334>;
+                                       required-opps = <&rpmhpd_opp_nom>,
+                                                       <&rpmhpd_opp_nom>;
+                               };
+
+                               opp-570000000 {
+                                       opp-hz = /bits/ 64 <570000000>;
+                                       required-opps = <&rpmhpd_opp_nom_l1>,
+                                                       <&rpmhpd_opp_nom_l1>;
+                               };
+
+                               opp-630000000 {
+                                       opp-hz = /bits/ 64 <630000000>;
+                                       required-opps = <&rpmhpd_opp_turbo>,
+                                                       <&rpmhpd_opp_turbo>;
+                               };
+                       };
+               };
+
+               videocc: clock-controller@aaf0000 {
+                       compatible = "qcom,sm8750-videocc";
+                       reg = <0x0 0x0aaf0000 0x0 0x10000>;
+                       clocks = <&bi_tcxo_div2>,
+                                <&gcc GCC_VIDEO_AHB_CLK>;
+                       power-domains = <&rpmhpd RPMHPD_MMCX>,
+                                       <&rpmhpd RPMHPD_MXC>;
+                       required-opps = <&rpmhpd_opp_low_svs>,
+                                       <&rpmhpd_opp_low_svs>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                pdc: interrupt-controller@b220000 {
                        compatible = "qcom,sm8750-pdc", "qcom,pdc";
                        reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;