drm/amd/display: Remove unused code

[why]
two sets of dccg_init:
one in dc/dccg, one in dc/hwss.
remove hwss's dccg_init for asics not use it.

Reviewed-by: Chris Park <chris.park@amd.com>
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index c8ff8ae85a03064a695262610e0613bf41cab25c..77ac7b22b8dc54809c808611a11bd195ce1e6035 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -3145,8 +3145,6 @@ void dcn20_fpga_init_hw(struct dc *dc)
        REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
        REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
 
-       hws->funcs.dccg_init(hws);
-
        REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
        REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
        if (REG(REFCLK_CNTL))

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
index d7ff55669bac00e5b8eeb00c1864196f0e84c032..5cbae0cdda9627d1fd8ff3d43f6514482ba34874 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c
@@ -143,7 +143,6 @@ static const struct hwseq_private_funcs dcn30_private_funcs = {
        .set_hdr_multiplier = dcn10_set_hdr_multiplier,
        .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
        .wait_for_blank_complete = dcn20_wait_for_blank_complete,
-       .dccg_init = dcn20_dccg_init,
        .set_blend_lut = dcn30_set_blend_lut,
        .set_shaper_3dlut = dcn20_set_shaper_3dlut,
 };

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c
index 8d7ceb7b32b86c2b224488695fce635065c14213..33cc48cd01962d1182e0f806661675d649974525 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c
@@ -140,7 +140,6 @@ static const struct hwseq_private_funcs dcn301_private_funcs = {
        .set_hdr_multiplier = dcn10_set_hdr_multiplier,
        .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
        .wait_for_blank_complete = dcn20_wait_for_blank_complete,
-       .dccg_init = dcn20_dccg_init,
        .set_blend_lut = dcn30_set_blend_lut,
        .set_shaper_3dlut = dcn20_set_shaper_3dlut,
 };

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
index 5a6a459da224adc7f92c6e4e4f99d3f13272ae8b..e56b9a46aecfe125d28e030f0f7ba7e0f9711bed 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c
@@ -144,7 +144,6 @@ static const struct hwseq_private_funcs dcn31_private_funcs = {
        .set_hdr_multiplier = dcn10_set_hdr_multiplier,
        .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
        .wait_for_blank_complete = dcn20_wait_for_blank_complete,
-       .dccg_init = dcn20_dccg_init,
        .set_blend_lut = dcn30_set_blend_lut,
        .set_shaper_3dlut = dcn20_set_shaper_3dlut,
        .setup_hpo_hw_control = dcn31_setup_hpo_hw_control,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
index 79faab1125d40b54a11e5093a23262c331ca37b5..9900c87b4567f5250b7936785b882fd96e5934f8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c
@@ -149,7 +149,6 @@ static const struct hwseq_private_funcs dcn314_private_funcs = {
        .set_hdr_multiplier = dcn10_set_hdr_multiplier,
        .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
        .wait_for_blank_complete = dcn20_wait_for_blank_complete,
-       .dccg_init = dcn20_dccg_init,
        .set_blend_lut = dcn30_set_blend_lut,
        .set_shaper_3dlut = dcn20_set_shaper_3dlut,
        .setup_hpo_hw_control = dcn31_setup_hpo_hw_control,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
index c19ef075c88231258f741b22d8c82e0910396bf0..849dae18b7384a4b09cc1e43fce0c6d658bf10f8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
@@ -154,7 +154,6 @@ static const struct hwseq_private_funcs dcn32_private_funcs = {
        .set_hdr_multiplier = dcn10_set_hdr_multiplier,
        .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
        .wait_for_blank_complete = dcn20_wait_for_blank_complete,
-       .dccg_init = dcn20_dccg_init,
        .set_mcm_luts = dcn32_set_mcm_luts,
        .program_mall_pipe_config = dcn32_program_mall_pipe_config,
        .update_force_pstate = dcn32_update_force_pstate,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index 81bd36f3381dbd91bd3729ff601f31c3bd261aa8..6ac8ad97cf13546d27a4653fef5ba1a93dde2032 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
@@ -164,7 +164,6 @@ static const struct hwseq_private_funcs dcn35_private_funcs = {
        .set_hdr_multiplier = dcn10_set_hdr_multiplier,
        .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
        .wait_for_blank_complete = dcn20_wait_for_blank_complete,
-       .dccg_init = dcn20_dccg_init,
        .set_mcm_luts = dcn32_set_mcm_luts,
        .setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
        .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index 09e60158f0b5a5aedfea5a11184f36231297f32b..04c260015eec36f40f924b1d0ddeeec7215d3b2a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -153,7 +153,6 @@ static const struct hwseq_private_funcs dcn351_private_funcs = {
        .set_hdr_multiplier = dcn10_set_hdr_multiplier,
        .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
        .wait_for_blank_complete = dcn20_wait_for_blank_complete,
-       .dccg_init = dcn20_dccg_init,
        .set_mcm_luts = dcn32_set_mcm_luts,
        .setup_hpo_hw_control = dcn35_setup_hpo_hw_control,
        .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index 162096ce0bdfb69e38621e067f97bbfac1f877b8..5d0dfb36f3e1bcddb4e137e96bf53d814c6d929b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -156,7 +156,6 @@ static const struct hwseq_private_funcs dcn401_private_funcs = {
        .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
        .verify_allow_pstate_change_high_sequence = dcn401_verify_allow_pstate_change_high_sequence,
        .wait_for_blank_complete = dcn20_wait_for_blank_complete,
-       .dccg_init = dcn20_dccg_init,
        .set_mcm_luts = dcn401_set_mcm_luts,
        .program_mall_pipe_config = dcn32_program_mall_pipe_config,
        .program_mall_pipe_config_sequence = dcn401_program_mall_pipe_config_sequence,