arm64: dts: qcom: Add Mahua SoC and CRD

Introduce support for the Mahua SoC and the CRD based on it. Some of
the notable differences are the absent CPU cluster, interconnect, TLMM,
thermal zones and adjusted PCIe west clocks. Everything else should
work as-is.

Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Co-developed-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Co-developed-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318124100.212992-4-gopikrishna.garmidi@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index a06621076f11bdddee62d9a01f9532ecf7b723e2..d141fcfaecbc0746bc5f1f21e13adccbe0f7e938 100644 (file)
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_QCOM)       += lemans-evk-camera.dtb
 lemans-evk-el2-dtbs := lemans-evk.dtb lemans-el2.dtbo
 
 dtb-$(CONFIG_ARCH_QCOM)        += lemans-evk-el2.dtb
+dtb-$(CONFIG_ARCH_QCOM)        += mahua-crd.dtb
 dtb-$(CONFIG_ARCH_QCOM)        += milos-fairphone-fp6.dtb
 dtb-$(CONFIG_ARCH_QCOM)        += monaco-evk.dtb
 

diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 5de4b28013210ff86caa15f8389426e9ff92f80c..bde287f645ee94116a489c55be3b7b80db3815e9 100644 (file)
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -282,7 +282,7 @@
                                };
                        };
 
-                       cluster2 {
+                       cpu_map_cluster2: cluster2 {
                                core0 {
                                        cpu = <&cpu12>;
                                };

diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/qcom/mahua-crd.dts
new file mode 100644 (file)
index 0000000..9c8244e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+
+#include "mahua.dtsi"
+#include "glymur-crd.dtsi"
+
+/delete-node/ &pmcx0102_d_e0;
+/delete-node/ &pmcx0102_d0_thermal;
+/delete-node/ &pmh0104_i_e0;
+/delete-node/ &pmh0104_i0_thermal;
+/delete-node/ &pmh0104_j_e0;
+/delete-node/ &pmh0104_j0_thermal;
+
+/ {
+       model = "Qualcomm Technologies, Inc. Mahua CRD";
+       compatible = "qcom,mahua-crd", "qcom,mahua";
+};

diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom/mahua.dtsi
new file mode 100644 (file)
index 0000000..7aa8d26
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/mahua.dtsi
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/* Mahua is heavily based on Glymur, with some meaningful differences */
+#include "glymur.dtsi"
+
+/delete-node/ &cluster2_pd;
+/delete-node/ &cpu_map_cluster2;
+/delete-node/ &cpu12;
+/delete-node/ &cpu13;
+/delete-node/ &cpu14;
+/delete-node/ &cpu15;
+/delete-node/ &cpu16;
+/delete-node/ &cpu17;
+/delete-node/ &cpu_pd12;
+/delete-node/ &cpu_pd13;
+/delete-node/ &cpu_pd14;
+/delete-node/ &cpu_pd15;
+/delete-node/ &cpu_pd16;
+/delete-node/ &cpu_pd17;
+/delete-node/ &tsens6;
+/delete-node/ &tsens7;
+
+&aggre1_noc {
+       compatible = "qcom,mahua-aggre1-noc", "qcom,glymur-aggre1-noc";
+};
+
+&aggre2_noc {
+       compatible = "qcom,mahua-aggre2-noc", "qcom,glymur-aggre2-noc";
+};
+
+&aggre3_noc {
+       compatible = "qcom,mahua-aggre3-noc", "qcom,glymur-aggre3-noc";
+};
+
+&aggre4_noc {
+       compatible = "qcom,mahua-aggre4-noc", "qcom,glymur-aggre4-noc";
+};
+
+&clk_virt {
+       compatible = "qcom,mahua-clk-virt", "qcom,glymur-clk-virt";
+};
+
+&cnoc_main {
+       compatible = "qcom,mahua-cnoc-main", "qcom,glymur-cnoc-main";
+};
+
+&config_noc {
+       compatible = "qcom,mahua-cnoc-cfg";
+};
+
+&hsc_noc {
+       compatible = "qcom,mahua-hscnoc";
+};
+
+&lpass_ag_noc {
+       compatible = "qcom,mahua-lpass-ag-noc", "qcom,glymur-lpass-ag-noc";
+};
+
+&lpass_lpiaon_noc {
+       compatible = "qcom,mahua-lpass-lpiaon-noc", "qcom,glymur-lpass-lpiaon-noc";
+};
+
+&lpass_lpicx_noc {
+       compatible = "qcom,mahua-lpass-lpicx-noc", "qcom,glymur-lpass-lpicx-noc";
+};
+
+&mc_virt {
+       compatible = "qcom,mahua-mc-virt";
+};
+
+&mmss_noc {
+       compatible = "qcom,mahua-mmss-noc", "qcom,glymur-mmss-noc";
+};
+
+&nsi_noc {
+       compatible = "qcom,mahua-nsinoc", "qcom,glymur-nsinoc";
+};
+
+&nsp_noc {
+       compatible = "qcom,mahua-nsp-noc", "qcom,glymur-nsp-noc";
+};
+
+&oobm_ss_noc {
+       compatible = "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc";
+};
+
+&pcie_east_anoc {
+       compatible = "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc";
+};
+
+&pcie_east_slv_noc {
+       compatible = "qcom,mahua-pcie-east-slv-noc", "qcom,glymur-pcie-east-slv-noc";
+};
+
+&pcie_west_anoc {
+       compatible = "qcom,mahua-pcie-west-anoc";
+       clocks = <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>,
+                <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>,
+                <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>;
+};
+
+&pcie_west_slv_noc {
+       compatible = "qcom,mahua-pcie-west-slv-noc";
+};
+
+&system_noc {
+       compatible = "qcom,mahua-system-noc", "qcom,glymur-system-noc";
+};
+
+&tlmm {
+       compatible = "qcom,mahua-tlmm";
+};
+
+&thermal_zones {
+       /delete-node/ aoss-6-thermal;
+       /delete-node/ aoss-7-thermal;
+       /delete-node/ cpu-2-0-0-thermal;
+       /delete-node/ cpu-2-0-1-thermal;
+       /delete-node/ cpu-2-1-0-thermal;
+       /delete-node/ cpu-2-1-1-thermal;
+       /delete-node/ cpu-2-2-0-thermal;
+       /delete-node/ cpu-2-2-1-thermal;
+       /delete-node/ cpu-2-3-0-thermal;
+       /delete-node/ cpu-2-3-1-thermal;
+       /delete-node/ cpu-2-4-0-thermal;
+       /delete-node/ cpu-2-4-1-thermal;
+       /delete-node/ cpu-2-5-0-thermal;
+       /delete-node/ cpu-2-5-1-thermal;
+       /delete-node/ cpullc-2-0-thermal;
+       /delete-node/ cpuillc-2-1-thermal;
+       /delete-node/ ddr-2-thermal;
+       /delete-node/ gpu-3-0-thermal;
+       /delete-node/ gpu-3-1-thermal;
+       /delete-node/ gpu-3-2-thermal;
+       /delete-node/ qmx-2-0-thermal;
+       /delete-node/ qmx-2-1-thermal;
+       /delete-node/ qmx-2-2-thermal;
+       /delete-node/ qmx-2-3-thermal;
+       /delete-node/ qmx-2-4-thermal;
+       /delete-node/ video-1-thermal;
+
+       ddr-1-thermal {
+               thermal-sensors = <&tsens1 7>;
+       };
+
+       video-0-thermal {
+               thermal-sensors = <&tsens1 8>;
+       };
+
+       nsphvx-0-thermal {
+               thermal-sensors = <&tsens4 1>;
+       };
+
+       nsphvx-1-thermal {
+               thermal-sensors = <&tsens4 2>;
+       };
+
+       nsphvx-2-thermal {
+               thermal-sensors = <&tsens4 3>;
+       };
+
+       nsphvx-3-thermal {
+               thermal-sensors = <&tsens4 4>;
+       };
+
+       nsphmx-0-thermal {
+               thermal-sensors = <&tsens4 5>;
+       };
+
+       nsphmx-1-thermal {
+               thermal-sensors = <&tsens4 6>;
+       };
+
+       nsphmx-2-thermal {
+               thermal-sensors = <&tsens4 7>;
+       };
+
+       nsphmx-3-thermal {
+               thermal-sensors = <&tsens4 8>;
+       };
+
+       camera-0-thermal {
+               thermal-sensors = <&tsens4 9>;
+       };
+
+       camera-1-thermal {
+               thermal-sensors = <&tsens4 10>;
+       };
+
+       gpu-0-0-thermal {
+               thermal-sensors = <&tsens5 1>;
+       };
+
+       gpu-0-1-thermal {
+               thermal-sensors = <&tsens5 2>;
+       };
+
+       gpu-0-2-thermal {
+               thermal-sensors = <&tsens5 3>;
+       };
+
+       gpu-1-0-thermal {
+               thermal-sensors = <&tsens5 4>;
+       };
+
+       gpu-1-1-thermal {
+               thermal-sensors = <&tsens5 5>;
+       };
+
+       gpu-1-2-thermal {
+               thermal-sensors = <&tsens5 6>;
+       };
+
+       gpu-2-0-thermal {
+               thermal-sensors = <&tsens5 7>;
+       };
+
+       gpu-2-1-thermal {
+               thermal-sensors = <&tsens5 8>;
+       };
+
+       gpu-2-2-thermal {
+               thermal-sensors = <&tsens5 9>;
+       };
+
+       gpuss-0-thermal {
+               thermal-sensors = <&tsens5 10>;
+       };
+
+       gpuss-1-thermal {
+               thermal-sensors = <&tsens5 11>;
+       };
+
+       gpuss-2-thermal {
+               thermal-sensors = <&tsens5 12>;
+
+               trips {
+                       trip-point0 {
+                               temperature = <90000>;
+                               hysteresis = <5000>;
+                               type = "hot";
+                       };
+
+                       gpuss-2-critical {
+                               temperature = <115000>;
+                               hysteresis = <1000>;
+                               type = "critical";
+                       };
+               };
+       };
+
+       gpuss-3-thermal {
+               thermal-sensors = <&tsens5 13>;
+
+               trips {
+                       trip-point0 {
+                               temperature = <90000>;
+                               hysteresis = <5000>;
+                               type = "hot";
+                       };
+
+                       gpuss-3-critical {
+                               temperature = <115000>;
+                               hysteresis = <1000>;
+                               type = "critical";
+                       };
+               };
+       };
+
+       gpuss-4-thermal {
+               thermal-sensors = <&tsens5 14>;
+
+               trips {
+                       trip-point0 {
+                               temperature = <90000>;
+                               hysteresis = <5000>;
+                               type = "hot";
+                       };
+
+                       gpuss-4-critical {
+                               temperature = <115000>;
+                               hysteresis = <1000>;
+                               type = "critical";
+                       };
+               };
+       };
+};
+
+&tsens4 {
+       #qcom,sensors = <11>;
+};
+
+&tsens5 {
+       #qcom,sensors = <15>;
+};
+

diff --git a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi
index c3ccd2b756099cc04747d8bdf63cd6944897ac27..db2da9ef4f01945950a892a47aecf880e5608d1a 100644 (file)
--- a/arch/arm64/boot/dts/qcom/pmcx0102.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmcx0102.dtsi
@@ -46,7 +46,7 @@
                        };
                };
 
-               pmcx0102-d0-thermal {
+               pmcx0102_d0_thermal: pmcx0102-d0-thermal {
                        polling-delay-passive = <100>;
                        thermal-sensors = <&pmcx0102_d_e0_temp_alarm>;
 

diff --git a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi
index d89cceda53a3ff0ce06e85d3a7281bf156099782..7a1e5f355c175913a38d536a1ca13d870049b741 100644 (file)
--- a/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmh0104-glymur.dtsi
@@ -8,7 +8,7 @@
 
 /{
        thermal_zones {
-               pmh0104-i0-thermal {
+               pmh0104_i0_thermal: pmh0104-i0-thermal {
                        polling-delay-passive = <100>;
                        thermal-sensors = <&pmh0104_i_e0_temp_alarm>;
 
@@ -27,7 +27,7 @@
                        };
                };
 
-               pmh0104-j0-thermal {
+               pmh0104_j0_thermal: pmh0104-j0-thermal {
                        polling-delay-passive = <100>;
                        thermal-sensors = <&pmh0104_j_e0_temp_alarm>;