]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
net/mlx5: Check capability for fw_reset
authorMoshe Shemesh <moshe@nvidia.com>
Sun, 28 Jan 2024 18:43:58 +0000 (20:43 +0200)
committerSasha Levin <sashal@kernel.org>
Fri, 15 Mar 2024 14:48:15 +0000 (10:48 -0400)
[ Upstream commit 5e6107b499f3fc4748109e1d87fd9603b34f1e0d ]

Functions which can't access MFRL (Management Firmware Reset Level)
register, have no use of fw_reset structures or events. Remove fw_reset
structures allocation and registration for fw reset events notifications
for these functions.

Having the devlink param enable_remote_dev_reset on functions that don't
have this capability is misleading as these functions are not allowed to
influence the reset flow. Hence, this patch removes this parameter for
such functions.

In addition, return not supported on devlink reload action fw_activate
for these functions.

Fixes: 38b9f903f22b ("net/mlx5: Handle sync reset request event")
Signed-off-by: Moshe Shemesh <moshe@nvidia.com>
Reviewed-by: Aya Levin <ayal@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/net/ethernet/mellanox/mlx5/core/devlink.c
drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c
include/linux/mlx5/mlx5_ifc.h

index af8460bb257b93e21f556512014a974f0ddef63a..1bccb5633ab4bec19da9a3300d1233fe38f85a76 100644 (file)
@@ -168,6 +168,12 @@ static int mlx5_devlink_reload_down(struct devlink *devlink, bool netns_change,
                return -EOPNOTSUPP;
        }
 
+       if (action == DEVLINK_RELOAD_ACTION_FW_ACTIVATE &&
+           !dev->priv.fw_reset) {
+               NL_SET_ERR_MSG_MOD(extack, "FW activate is unsupported for this function");
+               return -EOPNOTSUPP;
+       }
+
        if (mlx5_core_is_pf(dev) && pci_num_vf(pdev))
                NL_SET_ERR_MSG_MOD(extack, "reload while VFs are present is unfavorable");
 
index c4e19d627da2148bd1fab3b6f388358320ecb9d0..3a9cdf79403ae9deb1c3be6f0704f09ff5af4ab7 100644 (file)
@@ -679,19 +679,30 @@ void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev)
 {
        struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 
+       if (!fw_reset)
+               return;
+
        MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT);
        mlx5_eq_notifier_register(dev, &fw_reset->nb);
 }
 
 void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev)
 {
-       mlx5_eq_notifier_unregister(dev, &dev->priv.fw_reset->nb);
+       struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
+
+       if (!fw_reset)
+               return;
+
+       mlx5_eq_notifier_unregister(dev, &fw_reset->nb);
 }
 
 void mlx5_drain_fw_reset(struct mlx5_core_dev *dev)
 {
        struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 
+       if (!fw_reset)
+               return;
+
        set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags);
        cancel_work_sync(&fw_reset->fw_live_patch_work);
        cancel_work_sync(&fw_reset->reset_request_work);
@@ -709,9 +720,13 @@ static const struct devlink_param mlx5_fw_reset_devlink_params[] = {
 
 int mlx5_fw_reset_init(struct mlx5_core_dev *dev)
 {
-       struct mlx5_fw_reset *fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL);
+       struct mlx5_fw_reset *fw_reset;
        int err;
 
+       if (!MLX5_CAP_MCAM_REG(dev, mfrl))
+               return 0;
+
+       fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL);
        if (!fw_reset)
                return -ENOMEM;
        fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events");
@@ -747,6 +762,9 @@ void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev)
 {
        struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 
+       if (!fw_reset)
+               return;
+
        devl_params_unregister(priv_to_devlink(dev),
                               mlx5_fw_reset_devlink_params,
                               ARRAY_SIZE(mlx5_fw_reset_devlink_params));
index 643e9ba4e64bd4db52d25b006880c2353c3b7358..58128de5dbdda75587b8b55096d64eaa2e8065c9 100644 (file)
@@ -10154,7 +10154,9 @@ struct mlx5_ifc_mcam_access_reg_bits {
 
        u8         regs_63_to_46[0x12];
        u8         mrtc[0x1];
-       u8         regs_44_to_32[0xd];
+       u8         regs_44_to_41[0x4];
+       u8         mfrl[0x1];
+       u8         regs_39_to_32[0x8];
 
        u8         regs_31_to_10[0x16];
        u8         mtmp[0x1];