drm/amdkfd: fix partitioned gfx12 address watch enablement

GFX 12 devices that support spatial partitioning should use the WREG32
per XCC macro when updating address watch settings, similar to GFX 9
devices that support spatial partitioning.

Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Mukul Joshi <mukul.joshi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
index 14e4c60b9d79ecdb54f075538cba9dd18fbc9ae5..965c7e688535ab7d0d9b6ac6c0cd08bbf9cc3586 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c
@@ -347,13 +347,13 @@ static uint32_t kgd_gfx_v12_1_set_address_watch(struct amdgpu_device *adev,
                        VALID,
                        1);
 
-       WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_H) +
+       WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_H) +
                        (watch_id * TCP_WATCH_STRIDE)),
-                       watch_address_high);
+                       watch_address_high, inst);
 
-       WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_L) +
+       WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_L) +
                        (watch_id * TCP_WATCH_STRIDE)),
-                       watch_address_low);
+                       watch_address_low, inst);
 
        return watch_address_cntl;
 }