backport: re PR middle-end/45472 ([Middle-end volatile semantics] ICE: in move_op_asc...

        Backport from mainline
        2013-02-27  Andrey Belevantsev  <abel@ispras.ru>

        PR middle-end/45472

        * sel-sched-ir.c (merge_expr): Also change vinsn of merged expr
        when the may_trap_p bit of the exprs being merged differs.
        Reorder tests for speculativeness in the logical and operator.

        Backport from mainline
         2013-03-05  Jakub Jelinek  <jakub@redhat.com>

        PR middle-end/56461
        * sel-sched-ir.c (free_sched_pools): Release
        succs_info_pool.stack[succs_info_pool.max_top] vectors too
        if succs_info_pool.max_top isn't -1.

        Backport from mainline
        2013-02-27  Andrey Belevantsev  <abel@ispras.ru>

        PR middle-end/45472
        * gcc.dg/pr45472.c: New test.

From-SVN: r197302

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e6f20740f64cd15274c94d0a0ad25c36f38b0e16..9015461bfaf29f29856b7012883d0934ad52c60b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,22 @@
+2013-04-01  Andrey Belevantsev  <abel@ispras.ru>
+
+       Backport from mainline
+       2013-02-27  Andrey Belevantsev  <abel@ispras.ru>
+
+       PR middle-end/45472
+       
+       * sel-sched-ir.c (merge_expr): Also change vinsn of merged expr
+       when the may_trap_p bit of the exprs being merged differs.
+       Reorder tests for speculativeness in the logical and operator.
+
+       Backport from mainline
+        2013-03-05  Jakub Jelinek  <jakub@redhat.com>
+        
+       PR middle-end/56461
+       * sel-sched-ir.c (free_sched_pools): Release
+       succs_info_pool.stack[succs_info_pool.max_top] vectors too
+       if succs_info_pool.max_top isn't -1.
+
 2013-04-01  Andrey Belevantsev  <abel@ispras.ru>
 
        Backport from mainline

diff --git a/gcc/sel-sched-ir.c b/gcc/sel-sched-ir.c
index 41440d894258d938006e5dd269c25f74d09101d2..38c817eca370684a170b523bb282583a8e233ebc 100644 (file)
--- a/gcc/sel-sched-ir.c
+++ b/gcc/sel-sched-ir.c
@@ -1857,8 +1857,12 @@ merge_expr (expr_t to, expr_t from, insn_t split_point)
   /* Make sure that speculative pattern is propagated into exprs that
      have non-speculative one.  This will provide us with consistent
      speculative bits and speculative patterns inside expr.  */
-  if (EXPR_SPEC_DONE_DS (to) == 0
-      && EXPR_SPEC_DONE_DS (from) != 0)
+  if ((EXPR_SPEC_DONE_DS (from) != 0
+       && EXPR_SPEC_DONE_DS (to) == 0)
+      /* Do likewise for volatile insns, so that we always retain
+        the may_trap_p bit on the resulting expression.  */
+      || (VINSN_MAY_TRAP_P (EXPR_VINSN (from))
+         && !VINSN_MAY_TRAP_P (EXPR_VINSN (to))))
     change_vinsn_in_expr (to, EXPR_VINSN (from));
 
   merge_expr_data (to, from, split_point);
@@ -4876,7 +4880,7 @@ free_sched_pools (void)
 
   free_alloc_pool (sched_lists_pool);
   gcc_assert (succs_info_pool.top == -1);
-  for (i = 0; i < succs_info_pool.max_top; i++)
+  for (i = 0; i <= succs_info_pool.max_top; i++)
     {
       VEC_free (rtx, heap, succs_info_pool.stack[i].succs_ok);
       VEC_free (rtx, heap, succs_info_pool.stack[i].succs_other);

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b502eac159bdbc3b8d06151bf391fd99001e68cf..5511389c779c44f9985c7570a5269a5a163edd00 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2013-04-01  Andrey Belevantsev  <abel@ispras.ru>
+
+       Backport from mainline
+       2013-02-27  Andrey Belevantsev  <abel@ispras.ru>
+       
+       PR middle-end/45472
+       * gcc.dg/pr45472.c: New test.
+
 2013-03-22  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR target/56560

diff --git a/gcc/testsuite/gcc.dg/pr45472.c b/gcc/testsuite/gcc.dg/pr45472.c
new file mode 100644 (file)
index 0000000..46a6373
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr45472.c
@@ -0,0 +1,84 @@
+/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+/* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */
+
+struct S
+{
+  volatile long vl;
+  int i;
+};
+struct S s1, s2;
+
+void
+foo (int j, int c)
+{
+  int i;
+  for (i = 0; i <= j; i++)
+    {
+      if (c)
+       s2.vl += s1.vl;
+      s1 = s2;
+    }
+}
+/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+/* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */
+
+struct S
+{
+  volatile long vl;
+  int i;
+};
+struct S s1, s2;
+
+void
+foo (int j, int c)
+{
+  int i;
+  for (i = 0; i <= j; i++)
+    {
+      if (c)
+       s2.vl += s1.vl;
+      s1 = s2;
+    }
+}
+/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+/* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */
+
+struct S
+{
+  volatile long vl;
+  int i;
+};
+struct S s1, s2;
+
+void
+foo (int j, int c)
+{
+  int i;
+  for (i = 0; i <= j; i++)
+    {
+      if (c)
+       s2.vl += s1.vl;
+      s1 = s2;
+    }
+}
+/* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+/* { dg-options "-O -fschedule-insns2 -fselective-scheduling2" } */
+
+struct S
+{
+  volatile long vl;
+  int i;
+};
+struct S s1, s2;
+
+void
+foo (int j, int c)
+{
+  int i;
+  for (i = 0; i <= j; i++)
+    {
+      if (c)
+       s2.vl += s1.vl;
+      s1 = s2;
+    }
+}