RISC-V: Add pattern for vector-scalar single-width floating-point reverse sub

This pattern enables the combine pass (or late-combine, depending on the case)
to merge a vec_duplicate into a minus RTL instruction. The vec_duplicate is the
minuend operand.

Before this patch, we have two instructions, e.g.:
  vfmv.v.f       v2,fa0
  vfsub.vv       v1,v2,v1

After, we get only one:
  vfrsub.vf      v1,v1,fa0

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*vfrsub_vf_<mode>): New pattern to
	combine vec_duplicate + vfsub.vv into vfrsub.vf.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfrsub.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: Add data for
	vfrsub.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f64.c: New test.

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index f4d13ca356842bcdbe40da48594c9192754caf2b..1c1cf76995b4a81bdc915cf8fc88def74cf6df8b 100644 (file)
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -2207,3 +2207,23 @@
   }
   [(set_attr "type" "vfalu")]
 )
+
+;; vfrsub.vf
+(define_insn_and_split "*vfrsub_vf_<mode>"
+  [(set (match_operand:V_VLSF 0 "register_operand")
+    (minus:V_VLSF
+      (vec_duplicate:V_VLSF
+        (match_operand:<VEL> 2 "register_operand"))
+      (match_operand:V_VLSF 1 "register_operand")))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+  {
+    riscv_vector::emit_vlmax_insn (code_for_pred_reverse_scalar (MINUS,
+                                                                <MODE>mode),
+                                  riscv_vector::BINARY_OP_FRM_DYN, operands);
+    DONE;
+  }
+  [(set_attr "type" "vfalu")]
+)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
index 002d091c3adcf46778349ffa668299e10024744f..53969931032eea674a075f1cf06cf416a4e493dc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
@@ -20,6 +20,7 @@ DEF_VF_BINOP_CASE_0 (_Float16, *, mul)
 DEF_VF_BINOP_CASE_0 (_Float16, +, add)
 DEF_VF_BINOP_CASE_0 (_Float16, -, sub)
 DEF_VF_BINOP_REVERSE_CASE_0 (_Float16, /, rdiv)
+DEF_VF_BINOP_REVERSE_CASE_0 (_Float16, -, rsub)
 DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min)
 DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min)
 DEF_VF_BINOP_CASE_2_WRAP (_Float16, MAX_FUNC_0_WRAP (_Float16), max)
@@ -42,6 +43,7 @@ DEF_VF_BINOP_WIDEN_CASE_0 (_Float16, float, *, mul)
 /* { dg-final { scan-assembler-times {vfadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfsub.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfrsub.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
 /* { dg-final { scan-assembler-times {vfmax.vf} 2 } } */
 /* { dg-final { scan-assembler-times {vfwmul.vf} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
index c8b323b63e799054545b2b3ce40007c8b19da4c5..9756184347b465578e39e6c34505a52f2e1ac10c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
@@ -20,6 +20,7 @@ DEF_VF_BINOP_CASE_0 (float, *, mul)
 DEF_VF_BINOP_CASE_0 (float, +, add)
 DEF_VF_BINOP_CASE_0 (float, -, sub)
 DEF_VF_BINOP_REVERSE_CASE_0 (float, /, rdiv)
+DEF_VF_BINOP_REVERSE_CASE_0 (float, -, rsub)
 DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_0_WRAP (float), min)
 DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_1_WRAP (float), min)
 DEF_VF_BINOP_CASE_2_WRAP (float, MAX_FUNC_0_WRAP (float), max)
@@ -42,6 +43,7 @@ DEF_VF_BINOP_WIDEN_CASE_0 (float, double, *, mul)
 /* { dg-final { scan-assembler-times {vfadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfsub.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfrsub.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
 /* { dg-final { scan-assembler-times {vfmax.vf} 2 } } */
 /* { dg-final { scan-assembler-times {vfwmul.vf} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
index 0d04b9231181d9c93ac023fc3173ae2f1736c7bc..12e32160a57722790d24a757f2730f46a343389a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
@@ -16,6 +16,7 @@ DEF_VF_BINOP_CASE_0 (double, *, mul)
 DEF_VF_BINOP_CASE_0 (double, +, add)
 DEF_VF_BINOP_CASE_0 (double, -, sub)
 DEF_VF_BINOP_REVERSE_CASE_0 (double, /, rdiv)
+DEF_VF_BINOP_REVERSE_CASE_0 (double, -, rsub)
 DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_0_WRAP (double), min)
 DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_1_WRAP (double), min)
 DEF_VF_BINOP_CASE_2_WRAP (double, MAX_FUNC_0_WRAP (double), max)
@@ -33,5 +34,6 @@ DEF_VF_BINOP_CASE_2_WRAP (double, MAX_FUNC_1_WRAP (double), max)
 /* { dg-final { scan-assembler-times {vfadd.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfsub.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfrsub.vf} 1 } } */
 /* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
 /* { dg-final { scan-assembler-times {vfmax.vf} 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
index 05361d8191c0d3e013d3af78a1e38471d39404f8..1712076031ddd0e6c42950ca612d15d4253392a7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
@@ -19,6 +19,7 @@
 /* { dg-final { scan-assembler-not {vfadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler-not {vfrsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
 /* { dg-final { scan-assembler-not {vfmax.vf} } } */
 /* { dg-final { scan-assembler-not {vfwmul.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
index 085d8727dacac60d99f38506cf58e476d0ed5961..2938bfbc1e35f484b3a06dd76b0f0e2ed9646fbf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
@@ -19,6 +19,7 @@
 /* { dg-final { scan-assembler-not {vfadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler-not {vfrsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
 /* { dg-final { scan-assembler-not {vfmax.vf} } } */
 /* { dg-final { scan-assembler-not {vfwmul.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
index 49ad3863a213573ff836a99c2c87c3ca2d23ba24..b770c458f86b9578481ea35159f654344eea69fd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
@@ -15,5 +15,6 @@
 /* { dg-final { scan-assembler-not {vfadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler-not {vfrsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
 /* { dg-final { scan-assembler-not {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
index e1d7730ec239d524111cf7de878ab6f59d26c28f..54db9809fe9e98b39efb05f50b09f45a7079cce7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
@@ -20,6 +20,7 @@ DEF_VF_BINOP_CASE_1 (_Float16, *, mul, VF_BINOP_BODY_X128)
 DEF_VF_BINOP_CASE_1 (_Float16, +, add, VF_BINOP_BODY_X128)
 DEF_VF_BINOP_CASE_1 (_Float16, -, sub, VF_BINOP_BODY_X128)
 DEF_VF_BINOP_REVERSE_CASE_1 (_Float16, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
+DEF_VF_BINOP_REVERSE_CASE_1 (_Float16, -, rsub, VF_BINOP_REVERSE_BODY_X128)
 DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min,
                          VF_BINOP_FUNC_BODY_X128)
 DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min,
@@ -46,6 +47,7 @@ DEF_VF_BINOP_WIDEN_CASE_1 (_Float16, float, *, mul)
 /* { dg-final { scan-assembler {vfadd.vf} } } */
 /* { dg-final { scan-assembler {vfsub.vf} } } */
 /* { dg-final { scan-assembler {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler {vfrsub.vf} } } */
 /* { dg-final { scan-assembler {vfmin.vf} } } */
 /* { dg-final { scan-assembler {vfmax.vf} } } */
 /* { dg-final { scan-assembler {vfwmul.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
index bef9a2d41cbf3f00cd8aab6035e66f10d61deed1..97791cd83ce3692cd9a523a50cd7eaaf36e51a01 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
@@ -20,6 +20,7 @@ DEF_VF_BINOP_CASE_1 (float, *, mul, VF_BINOP_BODY_X128)
 DEF_VF_BINOP_CASE_1 (float, +, add, VF_BINOP_BODY_X128)
 DEF_VF_BINOP_CASE_1 (float, -, sub, VF_BINOP_BODY_X128)
 DEF_VF_BINOP_REVERSE_CASE_1 (float, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
+DEF_VF_BINOP_REVERSE_CASE_1 (float, -, rsub, VF_BINOP_REVERSE_BODY_X128)
 DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_0_WRAP (float), min,
                          VF_BINOP_FUNC_BODY_X128)
 DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_1_WRAP (float), min,
@@ -46,6 +47,7 @@ DEF_VF_BINOP_WIDEN_CASE_1 (float, double, *, mul)
 /* { dg-final { scan-assembler {vfadd.vf} } } */
 /* { dg-final { scan-assembler {vfsub.vf} } } */
 /* { dg-final { scan-assembler {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler {vfrsub.vf} } } */
 /* { dg-final { scan-assembler {vfmin.vf} } } */
 /* { dg-final { scan-assembler {vfmax.vf} } } */
 /* { dg-final { scan-assembler {vfwmul.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
index 861da77a82bdbef6e666f0c486d2348019d91897..7199444ee3dc703a1b30d6eea2a0c70ea6b31b63 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
@@ -16,6 +16,7 @@ DEF_VF_BINOP_CASE_1 (double, *, mul, VF_BINOP_BODY_X128)
 DEF_VF_BINOP_CASE_1 (double, +, add, VF_BINOP_BODY_X128)
 DEF_VF_BINOP_CASE_1 (double, -, sub, VF_BINOP_BODY_X128)
 DEF_VF_BINOP_REVERSE_CASE_1 (double, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
+DEF_VF_BINOP_REVERSE_CASE_1 (double, -, rsub, VF_BINOP_REVERSE_BODY_X128)
 DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_0_WRAP (double), min,
                          VF_BINOP_FUNC_BODY_X128)
 DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_1_WRAP (double), min,
@@ -37,5 +38,6 @@ DEF_VF_BINOP_CASE_3_WRAP (double, MAX_FUNC_1_WRAP (double), max,
 /* { dg-final { scan-assembler {vfadd.vf} } } */
 /* { dg-final { scan-assembler {vfsub.vf} } } */
 /* { dg-final { scan-assembler {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler {vfrsub.vf} } } */
 /* { dg-final { scan-assembler {vfmin.vf} } } */
 /* { dg-final { scan-assembler {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
index 19456dcb16c5e0201b07fa96d5cd7a1b47c9a1ed..b5c94148d3712abae6f931c48f6bdf2ab48bdfb9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
@@ -19,6 +19,7 @@
 /* { dg-final { scan-assembler-not {vfadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler-not {vfrsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
 /* { dg-final { scan-assembler-not {vfmax.vf} } } */
 /* { dg-final { scan-assembler-not {vfwmul.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
index 9c3a59f28ef839d01dc608478edc61111d03b99c..086cf75fe418be60c2ceb871085a3dc11804032e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
@@ -19,6 +19,7 @@
 /* { dg-final { scan-assembler-not {vfadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler-not {vfrsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
 /* { dg-final { scan-assembler-not {vfmax.vf} } } */
 /* { dg-final { scan-assembler-not {vfwmul.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
index 14cf691ca6fcba61b3d03dcb1dcb727880c57ebf..4679799bbbeb02854a57c5f26cbcbc2a476f1529 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
@@ -15,5 +15,6 @@
 /* { dg-final { scan-assembler-not {vfadd.vf} } } */
 /* { dg-final { scan-assembler-not {vfsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
+/* { dg-final { scan-assembler-not {vfrsub.vf} } } */
 /* { dg-final { scan-assembler-not {vfmin.vf} } } */
 /* { dg-final { scan-assembler-not {vfmax.vf} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
index d7f8d1dcd458aea70419283baa3b45ec1d558f6c..60dd0ce94b4d9e264f0672bf78279296d370cf1e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
@@ -594,6 +594,153 @@ double TEST_BINOP_DATA(double, rdiv)[][4][N] =
   },
 };
 
+_Float16 TEST_BINOP_DATA(_Float16, rsub)[][4][N] =
+{
+  {
+    { 0x1.fd40000000000p+6f16 },
+    {
+    0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16,
+    0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16,
+    0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16,
+    0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16,
+    },
+    {
+    0x1.9940000000000p+6f16, 0x1.9940000000000p+6f16, 0x1.9940000000000p+6f16, 0x1.9940000000000p+6f16,
+    0x1.12c0000000000p+4f16, 0x1.12c0000000000p+4f16, 0x1.12c0000000000p+4f16, 0x1.12c0000000000p+4f16,
+    0x1.2ac0000000000p+6f16, 0x1.2ac0000000000p+6f16, 0x1.2ac0000000000p+6f16, 0x1.2ac0000000000p+6f16,
+    0x1.a140000000000p+6f16, 0x1.a140000000000p+6f16, 0x1.a140000000000p+6f16, 0x1.a140000000000p+6f16,
+    },
+  },
+  {
+    { 0x1.fd40000000000p+6f16 },
+    {
+    -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
+    0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16,
+    -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
+    -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
+    },
+    {
+    0x1.5380000000000p+7f16, 0x1.5380000000000p+7f16, 0x1.5380000000000p+7f16, 0x1.5380000000000p+7f16,
+    0x1.d180000000000p+3f16, 0x1.d180000000000p+3f16, 0x1.d180000000000p+3f16, 0x1.d180000000000p+3f16,
+    0x1.7f00000000000p+8f16, 0x1.7f00000000000p+8f16, 0x1.7f00000000000p+8f16, 0x1.7f00000000000p+8f16,
+    0x1.c900000000000p+7f16, 0x1.c900000000000p+7f16, 0x1.c900000000000p+7f16, 0x1.c900000000000p+7f16,
+    },
+  },
+  {
+    { -0x1.fd40000000000p+6f16 },
+    {
+    -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
+    -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
+    0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16,
+    -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
+    },
+    {
+    -0x1.7a40000000000p+6f16, -0x1.7a40000000000p+6f16, -0x1.7a40000000000p+6f16, -0x1.7a40000000000p+6f16,
+    0x1.cd40000000000p+6f16, 0x1.cd40000000000p+6f16, 0x1.cd40000000000p+6f16, 0x1.cd40000000000p+6f16,
+    -0x1.3180000000000p+7f16, -0x1.3180000000000p+7f16, -0x1.3180000000000p+7f16, -0x1.3180000000000p+7f16,
+    -0x1.78c0000000000p+6f16, -0x1.78c0000000000p+6f16, -0x1.78c0000000000p+6f16, -0x1.78c0000000000p+6f16,
+    },
+  },
+};
+
+float TEST_BINOP_DATA(float, rsub)[][4][N] =
+{
+  {
+    { 0x1.05bc2e0000000p+63f },
+    {
+    0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f,
+    0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f,
+    0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f,
+    0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f,
+    },
+    {
+    0x1.a780060000000p+62f, 0x1.a780060000000p+62f, 0x1.a780060000000p+62f, 0x1.a780060000000p+62f,
+    0x1.4b0ca80000000p+60f, 0x1.4b0ca80000000p+60f, 0x1.4b0ca80000000p+60f, 0x1.4b0ca80000000p+60f,
+    0x1.3902c20000000p+62f, 0x1.3902c20000000p+62f, 0x1.3902c20000000p+62f, 0x1.3902c20000000p+62f,
+    0x1.af8ca60000000p+62f, 0x1.af8ca60000000p+62f, 0x1.af8ca60000000p+62f, 0x1.af8ca60000000p+62f,
+    }
+  },
+  {
+    { 0x1.3d86160000000p+60f },
+    {
+    -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f,
+    0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f,
+    -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f,
+    -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f,
+    },
+    {
+    0x1.f2a3c60000000p+61f, 0x1.f2a3c60000000p+61f, 0x1.f2a3c60000000p+61f, 0x1.f2a3c60000000p+61f,
+    -0x1.73d7f60000000p+62f, -0x1.73d7f60000000p+62f, -0x1.73d7f60000000p+62f, -0x1.73d7f60000000p+62f,
+    0x1.13c9620000000p+64f, 0x1.13c9620000000p+64f, 0x1.13c9620000000p+64f, 0x1.13c9620000000p+64f,
+    0x1.e4342e0000000p+62f, 0x1.e4342e0000000p+62f, 0x1.e4342e0000000p+62f, 0x1.e4342e0000000p+62f,
+    },
+  },
+  {
+    { -0x1.3d86160000000p+60f },
+    {
+    -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f,
+    -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f,
+    0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f,
+    -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f,
+    },
+    {
+    0x1.9d9ca40000000p+59f, 0x1.9d9ca40000000p+59f, 0x1.9d9ca40000000p+59f, 0x1.9d9ca40000000p+59f,
+    0x1.bdc2d40000000p+63f, 0x1.bdc2d40000000p+63f, 0x1.bdc2d40000000p+63f, 0x1.bdc2d40000000p+63f,
+    -0x1.6a2dec0000000p+61f, -0x1.6a2dec0000000p+61f, -0x1.6a2dec0000000p+61f, -0x1.6a2dec0000000p+61f,
+    0x1.a8a15a0000000p+59f, 0x1.a8a15a0000000p+59f, 0x1.a8a15a0000000p+59f, 0x1.a8a15a0000000p+59f,
+    },
+  },
+};
+
+double TEST_BINOP_DATA(double, rsub)[][4][N] =
+{
+  {
+    { 0x1.ca3d8e6d80cbbp+510 },
+    {
+    0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508,
+    0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510,
+    0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509,
+    0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508,
+    },
+    {
+    0x1.664538d5bc21dp+510, 0x1.664538d5bc21dp+510, 0x1.664538d5bc21dp+510, 0x1.664538d5bc21dp+510,
+    0x1.1885a955eff10p+506, 0x1.1885a955eff10p+506, 0x1.1885a955eff10p+506, 0x1.1885a955eff10p+506,
+    0x1.ef8fe723bcf22p+509, 0x1.ef8fe723bcf22p+509, 0x1.ef8fe723bcf22p+509, 0x1.ef8fe723bcf22p+509,
+    0x1.6e51d7949b4e9p+510, 0x1.6e51d7949b4e9p+510, 0x1.6e51d7949b4e9p+510, 0x1.6e51d7949b4e9p+510,
+    },
+  },
+  {
+    { 0x1.ca3d8e6d80cbbp+510 },
+    {
+    -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509,
+    0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510,
+    -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511,
+    -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510,
+    },
+    {
+    0x1.3a16f6371ca58p+511, 0x1.3a16f6371ca58p+511, 0x1.3a16f6371ca58p+511, 0x1.3a16f6371ca58p+511,
+    0x1.c1045fb12de40p+504, 0x1.c1045fb12de40p+504, 0x1.c1045fb12de40p+504, 0x1.c1045fb12de40p+504,
+    0x1.728065d32d020p+512, 0x1.728065d32d020p+512, 0x1.728065d32d020p+512, 0x1.728065d32d020p+512,
+    0x1.af881bb6dfd6ap+511, 0x1.af881bb6dfd6ap+511, 0x1.af881bb6dfd6ap+511, 0x1.af881bb6dfd6ap+511,
+    },
+  },
+  {
+    { -0x1.ca3d8e6d80cbbp+510 },
+    {
+    -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509,
+    -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511,
+    0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508,
+    -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509,
+    },
+    {
+    -0x1.4728739ce255bp+510, -0x1.4728739ce255bp+510, -0x1.4728739ce255bp+510, -0x1.4728739ce255bp+510,
+    0x1.0054d0d202df0p+511, 0x1.0054d0d202df0p+511, 0x1.0054d0d202df0p+511, 0x1.0054d0d202df0p+511,
+    -0x1.17f97fb00fa24p+511, -0x1.17f97fb00fa24p+511, -0x1.17f97fb00fa24p+511, -0x1.17f97fb00fa24p+511,
+    -0x1.45c7dce9994ffp+510, -0x1.45c7dce9994ffp+510, -0x1.45c7dce9994ffp+510, -0x1.45c7dce9994ffp+510,
+    },
+  },
+};
+
 _Float16 TEST_BINOP_DATA(_Float16, min)[][4][N] =
 {
   {

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f16.c
new file mode 100644 (file)
index 0000000..7b424e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f16.c
@@ -0,0 +1,19 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T    _Float16
+#define NAME rsub
+
+DEF_VF_BINOP_REVERSE_CASE_0_WRAP (T, -, NAME)
+
+#define TEST_DATA                        TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T, NAME, out, in, f, n)
+
+#include "vf_binop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f32.c
new file mode 100644 (file)
index 0000000..e5fc9d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T    float
+#define NAME rsub
+
+DEF_VF_BINOP_REVERSE_CASE_0_WRAP (T, -, NAME)
+
+#define TEST_DATA                        TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T, NAME, out, in, f, n)
+
+#include "vf_binop_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f64.c
new file mode 100644 (file)
index 0000000..43d4cdd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfrsub-run-1-f64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T    double
+#define NAME rsub
+
+DEF_VF_BINOP_REVERSE_CASE_0_WRAP (T, -, NAME)
+
+#define TEST_DATA                        TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_REVERSE_CASE_0_WRAP(T, NAME, out, in, f, n)
+
+#include "vf_binop_run.h"