arm64: dts: freescale: imx8mp-var-som: Add EQoS support with MaxLinear PHY

Enable the EQoS Ethernet controller on the i.MX8MP VAR-SOM with the
integrated Maxlinear MXL86110 PHY. The PHY is connected to the EQOS
MDIO bus at address 4.

This patch adds:
- EQOS controller configuration with RGMII interface.
- Proper reset timings.
- PHY power supply regulators.
- RGMII pinmux configuration for all data, control and clock signals.
- LED configuration for link status indication via the LED subsystem
  under /sys/class/leds/, leveraging the support implemented in the.
  mxl86110 PHY driver (drivers/net/phy/mxl-86110.c).
  Two LEDs are defined to match the LED configuration on the Variscite
  VAR-SOM Carrier Boards:
    * LED@0: Yellow, netdev trigger.
    * LED@1: Green, netdev trigger.

The RGMII TX/RX delays are implemented in SOM via PCB passive
delays, so no software delay configuration is required.

Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
index b59da91fdd041f0630e54e7487b67388746fee72..29f080904482c53c0d04321d53135b51e7fc24c5 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi
@@ -55,6 +55,24 @@
                states = <3300000 0x0 1800000 0x1>;
                vin-supply = <&ldo5>;
        };
+
+       reg_phy_supply: regulator-phy-supply {
+               compatible = "regulator-fixed";
+               regulator-name = "phy-supply";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               regulator-enable-ramp-delay = <20000>;
+               gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+               regulator-always-on;
+       };
+
+       reg_phy_vddio: regulator-phy-vddio {
+               compatible = "regulator-fixed";
+               regulator-name = "vddio-1v8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+       };
 };
 
 &A53_0 {
@@ -73,6 +91,53 @@
        cpu-supply = <&buck2>;
 };
 
+&eqos {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_eqos>;
+       /*
+        * The required RGMII TX and RX 2ns delays are implemented directly
+        * in hardware via passive delay elements on the SOM PCB.
+        * No delay configuration is needed in software via PHY driver.
+        */
+       phy-mode = "rgmii";
+       phy-handle = <&ethphy0>;
+       status = "okay";
+
+       mdio {
+               compatible = "snps,dwmac-mdio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               ethphy0: ethernet-phy@4 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <4>;
+                       reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <100000>;
+                       vddio-supply = <&reg_phy_vddio>;
+
+                       leds {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               led@0 {
+                                       reg = <0>;
+                                       color = <LED_COLOR_ID_YELLOW>;
+                                       function = LED_FUNCTION_LAN;
+                                       linux,default-trigger = "netdev";
+                               };
+
+                               led@1 {
+                                       reg = <1>;
+                                       color = <LED_COLOR_ID_GREEN>;
+                                       function = LED_FUNCTION_LAN;
+                                       linux,default-trigger = "netdev";
+                               };
+                       };
+               };
+       };
+};
+
 &i2c1 {
        clock-frequency = <400000>;
        pinctrl-names = "default";
@@ -239,6 +304,27 @@
 
 &iomuxc {
 
+       pinctrl_eqos: eqosgrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                             0x2
+                       MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                           0x2
+                       MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0                       0x90
+                       MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1                       0x90
+                       MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2                       0x90
+                       MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3                       0x90
+                       MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK       0x90
+                       MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL                 0x90
+                       MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0                       0x16
+                       MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1                       0x16
+                       MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2                       0x16
+                       MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3                       0x16
+                       MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL                 0x16
+                       MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK       0x16
+                       MX8MP_IOMUXC_SD2_WP__GPIO2_IO20                                 0x10
+                       MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10                             0x150
+               >;
+       };
+
        pinctrl_i2c1: i2c1grp {
                fsl,pins = <
                        MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL                                0x400001c2