]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amdgpu/sdma: add query for CSA size and alignment
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 10 Oct 2025 19:54:49 +0000 (15:54 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 10 Dec 2025 22:38:26 +0000 (17:38 -0500)
Needed to query the CSA size and alignment for SDMA
user queues.

Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

index cb0f8e8a0000764c1a1615af066cc02e53234616..2bf365609775a268bbc2a850741c7d4d2b4d152c 100644 (file)
@@ -50,6 +50,11 @@ enum amdgpu_sdma_irq {
 
 #define NUM_SDMA(x) hweight32(x)
 
+struct amdgpu_sdma_csa_info {
+       u32 size;
+       u32 alignment;
+};
+
 struct amdgpu_sdma_funcs {
        int (*stop_kernel_queue)(struct amdgpu_ring *ring);
        int (*start_kernel_queue)(struct amdgpu_ring *ring);
@@ -139,6 +144,8 @@ struct amdgpu_sdma {
        struct list_head        reset_callback_list;
        bool                    no_user_submission;
        bool                    disable_uq;
+       void (*get_csa_info)(struct amdgpu_device *adev,
+                            struct amdgpu_sdma_csa_info *csa_info);
 };
 
 /*
index 4996d60751ef7c330c8696d9caa08a699ac830f2..f38c2bdd01e3c168c76efb9ef05b5a32b1c6e231 100644 (file)
@@ -1268,6 +1268,17 @@ static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev)
        }
 }
 
+/* all sizes are in bytes */
+#define SDMA6_CSA_SIZE       32
+#define SDMA6_CSA_ALIGNMENT  4
+
+static void sdma_v6_0_get_csa_info(struct amdgpu_device *adev,
+                                  struct amdgpu_sdma_csa_info *csa_info)
+{
+       csa_info->size = SDMA6_CSA_SIZE;
+       csa_info->alignment = SDMA6_CSA_ALIGNMENT;
+}
+
 static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block)
 {
        struct amdgpu_device *adev = ip_block->adev;
@@ -1300,6 +1311,7 @@ static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block)
        sdma_v6_0_set_irq_funcs(adev);
        sdma_v6_0_set_mqd_funcs(adev);
        sdma_v6_0_set_ras_funcs(adev);
+       adev->sdma.get_csa_info = &sdma_v6_0_get_csa_info;
 
        return 0;
 }
index 7fee98d377205a8a5d6938959bda79f2ef88b58b..d2a09e7a1bc279444fb208ca92993bce4e494486 100644 (file)
@@ -1253,6 +1253,17 @@ static void sdma_v7_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
        amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
 }
 
+/* all sizes are in bytes */
+#define SDMA7_CSA_SIZE       32
+#define SDMA7_CSA_ALIGNMENT  4
+
+static void sdma_v7_0_get_csa_info(struct amdgpu_device *adev,
+                                  struct amdgpu_sdma_csa_info *csa_info)
+{
+       csa_info->size = SDMA7_CSA_SIZE;
+       csa_info->alignment = SDMA7_CSA_ALIGNMENT;
+}
+
 static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block)
 {
        struct amdgpu_device *adev = ip_block->adev;
@@ -1286,6 +1297,7 @@ static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block)
        sdma_v7_0_set_vm_pte_funcs(adev);
        sdma_v7_0_set_irq_funcs(adev);
        sdma_v7_0_set_mqd_funcs(adev);
+       adev->sdma.get_csa_info = &sdma_v7_0_get_csa_info;
 
        return 0;
 }