csr->csrs[reg] = val;
}
+static inline bool kvm_guest_has_msgint(struct kvm_vcpu_arch *arch)
+{
+ return arch->cpucfg[1] & CPUCFG1_MSGINT;
+}
+
static inline bool kvm_guest_has_fpu(struct kvm_vcpu_arch *arch)
{
return arch->cpucfg[2] & CPUCFG2_FP;
if (priority < EXCCODE_INT_NUM)
irq = priority_to_irq[priority];
- if (cpu_has_msgint && (priority == INT_AVEC)) {
+ if (kvm_guest_has_msgint(&vcpu->arch) && (priority == INT_AVEC)) {
set_gcsr_estat(irq);
return 1;
}
if (priority < EXCCODE_INT_NUM)
irq = priority_to_irq[priority];
- if (cpu_has_msgint && (priority == INT_AVEC)) {
+ if (kvm_guest_has_msgint(&vcpu->arch) && (priority == INT_AVEC)) {
clear_gcsr_estat(irq);
return 1;
}
kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_DMWIN2);
kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_DMWIN3);
kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_LLBCTL);
- if (cpu_has_msgint) {
+
+ if (kvm_guest_has_msgint(&vcpu->arch)) {
kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ISR0);
kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ISR1);
kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ISR2);
kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN1);
kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN2);
kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN3);
- if (cpu_has_msgint) {
+
+ if (kvm_guest_has_msgint(&vcpu->arch)) {
kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ISR0);
kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ISR1);
kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ISR2);