backport: re PR target/79545 (gcc[5/6]: RS6000, xvcvuxdsp and xvcvsxdsp RTL defines...

gcc/ChangeLog:

2017-02-16  Carl Love  <cel@us.ibm.com>

   Backport from mainline commit r245460 on 2017-02-14

   PR 79545
   * config/rs6000/rs6000.c: Add case statement entry to make the xvcvuxdsp
   built-in argument unsigned.
   * config/rs6000/vsx.md: Fix the source and return operand types so they
   match the instruction definitions from the ISA document.  Fix typo
   in the instruction generation for the (define_insn "vsx_xvcvuxdsp"
   statement.

gcc/testsuite/ChangeLog:

2017-01-16  Carl Love  <cel@us.ibm.com>

   Backport from mainline commit r245460 on 2017-02-14

   PR 79545
   * gcc.target/powerpc/vsx-builtin-3.c: Add missing test case for the
   xvcvsxdsp and xvcvuxdsp instructions.

From-SVN: r245518

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c7452e1b3cc77703193acc88fec00c345ca526a1..fae5376837611c181704a2b1a2f676eba7d5cf73 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,15 @@
+2017-02-16  Carl Love  <cel@us.ibm.com>
+
+       Backport from mainline commit r245460 on 2017-02-14
+
+       PR 79545
+       * config/rs6000/rs6000.c: Add case statement entry to make the xvcvuxdsp
+       built-in argument unsigned.
+       * config/rs6000/vsx.md: Fix the source and return operand types so they
+       match the instruction definitions from the ISA document.  Fix typo
+       in the instruction generation for the (define_insn "vsx_xvcvuxdsp"
+       statement.
+
 2017-02-14  Martin Liska  <mliska@suse.cz>
 
        Backport from mainline

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 5bba64e9c07d6031d0a4d33f4baa30ec66a4e52c..234d277637b248e35631fef1c51f217476668c2c 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -15628,6 +15628,7 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
       break;
 
       /* unsigned args, signed return.  */
+    case VSX_BUILTIN_XVCVUXDSP:
     case VSX_BUILTIN_XVCVUXDDP_UNS:
     case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
       h.uns_p[1] = 1;

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a689c2b71e704edaa9e68bdd0c2771bcdb1c74ea..efbd3ecccb8ee70af71f4c21d1ccc5f350c6a1f1 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1501,19 +1501,19 @@
   [(set_attr "type" "vecdouble")])
 
 (define_insn "vsx_xvcvsxdsp"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wd,?wa")
-       (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
+       (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
                     UNSPEC_VSX_CVSXDSP))]
   "VECTOR_UNIT_VSX_P (V2DFmode)"
   "xvcvsxdsp %x0,%x1"
   [(set_attr "type" "vecfloat")])
 
 (define_insn "vsx_xvcvuxdsp"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wd,?wa")
-       (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wf,wa")]
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wd,?wa")
+       (unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wf,wa")]
                     UNSPEC_VSX_CVUXDSP))]
   "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvuxwdp %x0,%x1"
+  "xvcvuxdsp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
 ;; Convert from 32-bit to 64-bit types

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8eb2ec6301b63c95e34e8b4dde97d68314bb7ece..580c2f6459bdd223ced32cea1283e44b361dc3d2 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2017-01-16  Carl Love  <cel@us.ibm.com>
+
+       Backport from mainline commit r245460 on 2017-02-14
+
+       PR 79545
+       * gcc.target/powerpc/vsx-builtin-3.c: Add missing test case for the
+       xvcvsxdsp and xvcvuxdsp instructions.
+
 2017-02-06  Carl Love  <cel@us.ibm.com>
        * gcc.target/powerpc/builtins-3-p8.c:  Add new testfile for missing
        vec_packs built-in tests.

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
index f337c1c745bf20438244c7363159ef1142b9d4e3..ff5296c87e23121e3cf67c5e870617b8bbbf065a 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
@@ -35,6 +35,8 @@
 /* { dg-final { scan-assembler "xvcmpgesp" } } */
 /* { dg-final { scan-assembler "xxsldwi" } } */
 /* { dg-final { scan-assembler-not "call" } } */
+/* { dg-final { scan-assembler "xvcvsxdsp" } } */
+/* { dg-final { scan-assembler "xvcvuxdsp" } } */
 
 extern __vector int si[][4];
 extern __vector short ss[][4];
@@ -50,7 +52,9 @@ extern __vector __pixel p[][4];
 #ifdef __VSX__
 extern __vector double d[][4];
 extern __vector long sl[][4];
+extern __vector long long sll[][4];
 extern __vector unsigned long ul[][4];
+extern __vector unsigned long long ull[][4];
 extern __vector __bool long bl[][4];
 #endif
 
@@ -211,3 +215,22 @@ int do_xxsldwi (void)
   d[i][0] = __builtin_vsx_xxsldwi (d[i][1], d[i][2], 3); i++;
   return i;
 }
+
+int do_xvcvsxdsp (void)
+{
+  int i = 0;
+
+  f[i][0] = __builtin_vsx_xvcvsxdsp (sll[i][1]); i++;
+
+  return i;
+}
+
+int do_xvcvuxdsp (void)
+{
+  int i = 0;
+
+  f[i][0] = __builtin_vsx_xvcvuxdsp (ull[i][1]); i++;
+
+  return i;
+}
+