sim: rx: add missing break to memory write

It doesn't seem like we want to keep executing the next block of code
after processing the request.

diff --git a/sim/rx/mem.c b/sim/rx/mem.c
index 2cba4cb3662d95ff75d61474555619a017aac0ae..83e23023f94392bb2e67e55cb457e71a9504b214 100644 (file)
--- a/sim/rx/mem.c
+++ b/sim/rx/mem.c
@@ -324,6 +324,7 @@ mem_put_byte (unsigned int address, unsigned char value)
          halt_pipeline_stats ();
        else
          reset_pipeline_stats ();
+       break;
       }
 #endif