Add umc ecc error handling for gmc v12_1.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
return 0;
}
+int amdgpu_umc_uniras_process_ecc_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry)
+{
+ struct ras_ih_info ih_info = {0};
+
+ ih_info.block = RAS_BLOCK_ID__UMC;
+ amdgpu_ras_mgr_dispatch_interrupt(adev, &ih_info);
+ return 0;
+}
+
int amdgpu_umc_fill_error_record(struct ras_err_data *err_data,
uint64_t err_addr,
uint64_t retired_page,
int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry);
+int amdgpu_umc_uniras_process_ecc_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry);
int amdgpu_umc_fill_error_record(struct ras_err_data *err_data,
uint64_t err_addr,
uint64_t retired_page,
if (r)
return r;
- if ((amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 1, 0)) &&
- !amdgpu_sriov_vf(adev)) {
+ if (!amdgpu_sriov_vf(adev)) {
/* interrupt sent to DF. */
- r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0,
+ if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 0, 0))
+ r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0,
+ &adev->gmc.ecc_irq);
+ else
+ r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_DF, 0,
&adev->gmc.ecc_irq);
+
if (r)
return r;
}
.process = gmc_v12_1_process_interrupt,
};
+static const struct amdgpu_irq_src_funcs gmc_v12_1_ecc_funcs = {
+ .process = amdgpu_umc_uniras_process_ecc_irq,
+};
+
void gmc_v12_1_set_irq_funcs(struct amdgpu_device *adev)
{
adev->gmc.vm_fault.num_types = 1;
adev->gmc.vm_fault.funcs = &gmc_v12_1_irq_funcs;
+
+ adev->gmc.ecc_irq.num_types = 1;
+ adev->gmc.ecc_irq.funcs = &gmc_v12_1_ecc_funcs;
}
void gmc_v12_1_init_vram_info(struct amdgpu_device *adev)