]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/amdgpu: Add umc ecc error handling for gmc v12_1
authorYiPeng Chai <YiPeng.Chai@amd.com>
Mon, 8 Dec 2025 08:23:10 +0000 (16:23 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 17 Mar 2026 14:33:08 +0000 (10:33 -0400)
Add umc ecc error handling for gmc v12_1.

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c

index 4df0f9d5ad11bc48d6faa3e12273ba4a30d9c6c4..0238c2798de4ecf165d5604acc9312d7fbc363ad 100644 (file)
@@ -398,6 +398,17 @@ int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
        return 0;
 }
 
+int amdgpu_umc_uniras_process_ecc_irq(struct amdgpu_device *adev,
+                       struct amdgpu_irq_src *source,
+                       struct amdgpu_iv_entry *entry)
+{
+       struct ras_ih_info ih_info = {0};
+
+       ih_info.block = RAS_BLOCK_ID__UMC;
+       amdgpu_ras_mgr_dispatch_interrupt(adev, &ih_info);
+       return 0;
+}
+
 int amdgpu_umc_fill_error_record(struct ras_err_data *err_data,
                uint64_t err_addr,
                uint64_t retired_page,
index 28dff750c47e3d371bd2117b8aa33f2998ab01ce..8494a55ebf76c8aa44bc40c1eaa23cd84e9097e7 100644 (file)
@@ -161,6 +161,9 @@ int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev,
 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
                struct amdgpu_irq_src *source,
                struct amdgpu_iv_entry *entry);
+int amdgpu_umc_uniras_process_ecc_irq(struct amdgpu_device *adev,
+               struct amdgpu_irq_src *source,
+               struct amdgpu_iv_entry *entry);
 int amdgpu_umc_fill_error_record(struct ras_err_data *err_data,
                uint64_t err_addr,
                uint64_t retired_page,
index ac39011d1268c0d6148a50d16ebbfef26248f094..f1079bd8cf001788cfaee3f3f1c6034152bb9d46 100644 (file)
@@ -893,11 +893,15 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
        if (r)
                return r;
 
-       if ((amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 1, 0)) &&
-           !amdgpu_sriov_vf(adev)) {
+       if (!amdgpu_sriov_vf(adev)) {
                /* interrupt sent to DF. */
-               r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0,
+               if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 0, 0))
+                       r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0,
+                                     &adev->gmc.ecc_irq);
+               else
+                       r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_DF, 0,
                                      &adev->gmc.ecc_irq);
+
                if (r)
                        return r;
        }
index 5e3102d072c4c8b2c1cae4e3c765bf5182a2998a..38c366b9a88bdac12e5d6263eeb20e5be9f22acf 100644 (file)
@@ -624,10 +624,17 @@ static const struct amdgpu_irq_src_funcs gmc_v12_1_irq_funcs = {
        .process = gmc_v12_1_process_interrupt,
 };
 
+static const struct amdgpu_irq_src_funcs gmc_v12_1_ecc_funcs = {
+       .process = amdgpu_umc_uniras_process_ecc_irq,
+};
+
 void gmc_v12_1_set_irq_funcs(struct amdgpu_device *adev)
 {
        adev->gmc.vm_fault.num_types = 1;
        adev->gmc.vm_fault.funcs = &gmc_v12_1_irq_funcs;
+
+       adev->gmc.ecc_irq.num_types = 1;
+       adev->gmc.ecc_irq.funcs = &gmc_v12_1_ecc_funcs;
 }
 
 void gmc_v12_1_init_vram_info(struct amdgpu_device *adev)