[(set_attr "type" "crypto_sha3")]
)
-(define_insn_and_split "*eor3qdi4"
- [(set (match_operand:DI 0 "register_operand")
- (xor:DI
- (xor:DI
- (match_operand:DI 2 "register_operand")
- (match_operand:DI 3 "register_operand"))
- (match_operand:DI 1 "register_operand")))]
- "TARGET_SHA3"
- {@ [ cons: =0, 1, 2 , 3 ; attrs: type ]
- [ w , w, w , w ; crypto_sha3 ] eor3\t%0.16b, %1.16b, %2.16b, %3.16b
- [ &r , r, r0, r0 ; multiple ] #
- }
- "&& REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))"
- [(set (match_dup 4) (xor:DI (match_dup 2) (match_dup 3)))
- (set (match_dup 0) (xor:DI (match_dup 4) (match_dup 1)))]
- {
- if (reload_completed)
- operands[4] = operands[0];
- else if (can_create_pseudo_p ())
- operands[4] = gen_reg_rtx (DImode);
- else
- FAIL;
- }
-)
-
(define_insn "aarch64_rax1qv2di"
[(set (match_operand:V2DI 0 "register_operand" "=w")
(xor:V2DI
#define EOR3(x,y,z) ((x) ^ (y) ^ (z))
-/* Should not use EOR3 when inputs come from GP regs. */
-uint64_t eor3_d_gp (uint64_t a, uint64_t b, uint64_t c) { return EOR3 (a, b, c); }
-
-uint64x1_t eor3_d (uint64x1_t a, uint64x1_t b, uint64x1_t c) { return EOR3 (a, b, c); }
uint32x2_t bcax_s (uint32x2_t a, uint32x2_t b, uint32x2_t c) { return EOR3 (a, b, c); }
uint16x4_t bcax_h (uint16x4_t a, uint16x4_t b, uint16x4_t c) { return EOR3 (a, b, c); }
uint8x8_t bcax_b (uint8x8_t a, uint8x8_t b, uint8x8_t c) { return EOR3 (a, b, c); }
-/* { dg-final { scan-assembler-times {eor3\tv0.16b, v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b} 4 } } */
+/* { dg-final { scan-assembler-times {eor3\tv0.16b, v[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b} 3 } } */