/* Subroutines for insn-output.c for MIPS
Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
- 1999, 2000, 2001 Free Software Foundation, Inc.
+ 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Contributed by A. Lichnewsky, lich@inria.inria.fr.
Changes by Michael Meissner, meissner@osf.org.
64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
enum machine_mode));
static int m16_check_op PARAMS ((rtx, int, int, int));
static void block_move_loop PARAMS ((rtx, rtx,
- unsigned int,
+ unsigned int,
int,
rtx, rtx));
static void block_move_call PARAMS ((rtx, rtx, rtx));
ATTRIBUTE_NORETURN;
static int symbolic_expression_p PARAMS ((rtx));
static void mips_add_gc_roots PARAMS ((void));
+static enum processor_type mips_parse_cpu PARAMS ((const char *));
/* Global variables for machine-dependent things. */
static int prev_half_pic_ptrs = 0;
static int prev_half_pic_refs = 0;
-/* which cpu are we scheduling for */
-enum processor_type mips_cpu;
+/* Which cpu we are generating code for. */
+enum processor_type mips_arch;
-/* which instruction set architecture to use. */
+/* The target cpu for optimization and scheduling. */
+enum processor_type mips_tune;
+
+/* Which instruction set architecture to use. */
int mips_isa;
#ifdef MIPS_ABI_DEFAULT
#endif
/* Strings to hold which cpu and instruction set architecture to use. */
+const char *mips_arch_string; /* for -march=<xxx> */
+const char *mips_tune_string; /* for -mtune=<xxx> */
const char *mips_cpu_string; /* for -mcpu=<xxx> */
const char *mips_isa_string; /* for -mips{1,2,3,4} */
const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
just a way to avoid using up another bit in target_flags. */
const char *mips_no_mips16_string;
-/* This is only used to determine if an type size setting option was
+/* This is only used to determine if an type size setting option was
explicitly specified (-mlong64, -mint64, -mlong32). The specs
set this option if such an option is used. */
const char *mips_explicit_type_size_string;
mips_check_split (address, mode)
rtx address;
enum machine_mode mode;
-{
+{
/* ??? This is the same check used in simple_memory_operand.
We use it here because LO_SUM is not offsettable. */
if (GET_MODE_SIZE (mode) > (unsigned) UNITS_PER_WORD)
enum machine_mode mode;
int strict;
{
- return (strict
+ return (strict
? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
: GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
}
rtx xinsn;
int strict;
{
- if (TARGET_DEBUG_B_MODE)
- {
- GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
- strict ? "" : "not ");
- GO_DEBUG_RTX (xinsn);
- }
-
- /* Check for constant before stripping off SUBREG, so that we don't
- accept (subreg (const_int)) which will fail to reload. */
- if (CONSTANT_ADDRESS_P (xinsn)
+ if (TARGET_DEBUG_B_MODE)
+ {
+ GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
+ strict ? "" : "not ");
+ GO_DEBUG_RTX (xinsn);
+ }
+
+ /* Check for constant before stripping off SUBREG, so that we don't
+ accept (subreg (const_int)) which will fail to reload. */
+ if (CONSTANT_ADDRESS_P (xinsn)
&& ! (mips_split_addresses && mips_check_split (xinsn, mode))
- && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
- return 1;
-
- while (GET_CODE (xinsn) == SUBREG)
- xinsn = SUBREG_REG (xinsn);
-
- /* The mips16 can only use the stack pointer as a base register when
- loading SImode or DImode values. */
- if (GET_CODE (xinsn) == REG
- && mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
- return 1;
-
- if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
- {
- register rtx xlow0 = XEXP (xinsn, 0);
- register rtx xlow1 = XEXP (xinsn, 1);
-
- while (GET_CODE (xlow0) == SUBREG)
- xlow0 = SUBREG_REG (xlow0);
- if (GET_CODE (xlow0) == REG
+ && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
+ return 1;
+
+ while (GET_CODE (xinsn) == SUBREG)
+ xinsn = SUBREG_REG (xinsn);
+
+ /* The mips16 can only use the stack pointer as a base register when
+ loading SImode or DImode values. */
+ if (GET_CODE (xinsn) == REG
+ && mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
+ return 1;
+
+ if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
+ {
+ register rtx xlow0 = XEXP (xinsn, 0);
+ register rtx xlow1 = XEXP (xinsn, 1);
+
+ while (GET_CODE (xlow0) == SUBREG)
+ xlow0 = SUBREG_REG (xlow0);
+ if (GET_CODE (xlow0) == REG
&& mips_reg_mode_ok_for_base_p (xlow0, mode, strict)
&& mips_check_split (xlow1, mode))
- return 1;
- }
-
- if (GET_CODE (xinsn) == PLUS)
- {
- register rtx xplus0 = XEXP (xinsn, 0);
- register rtx xplus1 = XEXP (xinsn, 1);
- register enum rtx_code code0;
- register enum rtx_code code1;
-
- while (GET_CODE (xplus0) == SUBREG)
- xplus0 = SUBREG_REG (xplus0);
- code0 = GET_CODE (xplus0);
-
- while (GET_CODE (xplus1) == SUBREG)
- xplus1 = SUBREG_REG (xplus1);
- code1 = GET_CODE (xplus1);
-
- /* The mips16 can only use the stack pointer as a base register
- when loading SImode or DImode values. */
- if (code0 == REG
- && mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
- {
+ return 1;
+ }
+
+ if (GET_CODE (xinsn) == PLUS)
+ {
+ register rtx xplus0 = XEXP (xinsn, 0);
+ register rtx xplus1 = XEXP (xinsn, 1);
+ register enum rtx_code code0;
+ register enum rtx_code code1;
+
+ while (GET_CODE (xplus0) == SUBREG)
+ xplus0 = SUBREG_REG (xplus0);
+ code0 = GET_CODE (xplus0);
+
+ while (GET_CODE (xplus1) == SUBREG)
+ xplus1 = SUBREG_REG (xplus1);
+ code1 = GET_CODE (xplus1);
+
+ /* The mips16 can only use the stack pointer as a base register
+ when loading SImode or DImode values. */
+ if (code0 == REG
+ && mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
+ {
if (code1 == CONST_INT && SMALL_INT (xplus1))
return 1;
-
- /* On the mips16, we represent GP relative offsets in RTL.
- These are 16 bit signed values, and can serve as register
- offsets. */
- if (TARGET_MIPS16
- && mips16_gp_offset_p (xplus1))
- return 1;
-
- /* For some code sequences, you actually get better code by
- pretending that the MIPS supports an address mode of a
- constant address + a register, even though the real
- machine doesn't support it. This is because the
- assembler can use $r1 to load just the high 16 bits, add
- in the register, and fold the low 16 bits into the memory
- reference, whereas the compiler generates a 4 instruction
- sequence. On the other hand, CSE is not as effective.
- It would be a win to generate the lui directly, but the
- MIPS assembler does not have syntax to generate the
- appropriate relocation. */
-
- /* Also accept CONST_INT addresses here, so no else. */
- /* Reject combining an embedded PIC text segment reference
- with a register. That requires an additional
- instruction. */
- /* ??? Reject combining an address with a register for the MIPS
- 64 bit ABI, because the SGI assembler can not handle this. */
- if (!TARGET_DEBUG_A_MODE
- && (mips_abi == ABI_32
- || mips_abi == ABI_O64
- || mips_abi == ABI_EABI)
- && CONSTANT_ADDRESS_P (xplus1)
- && ! mips_split_addresses
- && (!TARGET_EMBEDDED_PIC
- || code1 != CONST
- || GET_CODE (XEXP (xplus1, 0)) != MINUS)
- /* When assembling for machines with 64 bit registers,
+
+ /* On the mips16, we represent GP relative offsets in RTL.
+ These are 16 bit signed values, and can serve as register
+ offsets. */
+ if (TARGET_MIPS16
+ && mips16_gp_offset_p (xplus1))
+ return 1;
+
+ /* For some code sequences, you actually get better code by
+ pretending that the MIPS supports an address mode of a
+ constant address + a register, even though the real
+ machine doesn't support it. This is because the
+ assembler can use $r1 to load just the high 16 bits, add
+ in the register, and fold the low 16 bits into the memory
+ reference, whereas the compiler generates a 4 instruction
+ sequence. On the other hand, CSE is not as effective.
+ It would be a win to generate the lui directly, but the
+ MIPS assembler does not have syntax to generate the
+ appropriate relocation. */
+
+ /* Also accept CONST_INT addresses here, so no else. */
+ /* Reject combining an embedded PIC text segment reference
+ with a register. That requires an additional
+ instruction. */
+ /* ??? Reject combining an address with a register for the MIPS
+ 64 bit ABI, because the SGI assembler can not handle this. */
+ if (!TARGET_DEBUG_A_MODE
+ && (mips_abi == ABI_32
+ || mips_abi == ABI_O64
+ || mips_abi == ABI_EABI)
+ && CONSTANT_ADDRESS_P (xplus1)
+ && ! mips_split_addresses
+ && (!TARGET_EMBEDDED_PIC
+ || code1 != CONST
+ || GET_CODE (XEXP (xplus1, 0)) != MINUS)
+ /* When assembling for machines with 64 bit registers,
the assembler will not sign-extend the constant "foo"
in "la x, foo(x)" */
&& (!TARGET_64BIT || (INTVAL (xplus1) > 0))
- && !TARGET_MIPS16)
- return 1;
- }
- }
-
- if (TARGET_DEBUG_B_MODE)
+ && !TARGET_MIPS16)
+ return 1;
+ }
+ }
+
+ if (TARGET_DEBUG_B_MODE)
GO_PRINTF ("Not a legitimate address\n");
-
+
/* The address was not legitimate. */
return 0;
}
rtx seq;
embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
-
+
/* Output code at function start to initialize the pseudo-reg. */
/* ??? We used to do this in FINALIZE_PIC, but that does not work for
inline functions, because it is called after RTL for the function
if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
abort ();
-
+
sprintf (volatile_buffer, "%%{%s%%}", ret);
ret = volatile_buffer;
}
op1 = SUBREG_REG (op1);
code1 = GET_CODE (op1);
}
-
+
/* Sanity check. */
if (GET_CODE (operands[1]) == SIGN_EXTEND
&& code1 != REG
or higher. For !TARGET_64BIT && gp registers we
need to avoid this by using two li instructions
instead. */
- if (ISA_HAS_64BIT_REGS
+ if (ISA_HAS_64BIT_REGS
&& ! TARGET_64BIT
&& ! FP_REG_P (regno0))
{
: "mt%0\t%.\n");
}
}
-
+
else if (code1 == CONST_INT && GET_MODE (op0) == DImode
&& GP_REG_P (regno0))
{
if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
abort ();
-
+
sprintf (volatile_buffer, "%%{%s%%}", ret);
ret = volatile_buffer;
}
return 4;
}
-/* Return nonzero if X is an address which needs a temporary register when
+/* Return nonzero if X is an address which needs a temporary register when
reloaded while generating PIC code. */
int
emit_insn (gen_rtx_SET (VOIDmode, reg,
gen_rtx (test_code == NE ? EQ : test_code,
CCmode, cmp0, cmp1)));
-
+
test_code = test_code == NE ? EQ : NE;
mode = CCmode;
cmp0 = reg;
}
else if (cmp_code == NE)
cmp_code = EQ, move_code = EQ;
-
+
if (mode == SImode || mode == DImode)
cmp_mode = mode;
else if (mode == SFmode || mode == DFmode)
else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES
&& align == (unsigned) UNITS_PER_WORD)
move_by_pieces (orig_dest, orig_src, bytes, align * BITS_PER_WORD);
-
+
else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES)
emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
dest_reg),
block_move_call (dest_reg, src_reg, bytes_rtx);
}
\f
-/* Emit load/stores for a small constant block_move.
+/* Emit load/stores for a small constant block_move.
operands[0] is the memory address of the destination.
operands[1] is the memory address of the source.
fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
fprintf (stderr, ", %d ) = ", named);
}
-
+
cum->last_arg_fp = 0;
switch (mode)
regno + FP_ARG_FIRST - GP_ARG_FIRST);
else
reg = gen_rtx_REG (word_mode, regno);
-
- XVECEXP (ret, 0, i)
+
+ XVECEXP (ret, 0, i)
= gen_rtx_EXPR_LIST (VOIDmode, reg,
GEN_INT (bitpos / BITS_PER_UNIT));
\f
/* Create the va_list data type.
We keep 3 pointers, and two offsets.
- Two pointers are to the overflow area, which starts at the CFA.
+ Two pointers are to the overflow area, which starts at the CFA.
One of these is constant, for addressing into the GPR save area below it.
The other is advanced up the stack through the overflow region.
The third pointer is to the GPR save area. Since the FPR save area
is just below it, we can address FPR slots off this pointer.
We also keep two one-byte offsets, which are to be subtracted from the
constant pointers to yield addresses in the GPR and FPR save areas.
- These are downcounted as float or non-float arguments are used,
- and when they get to zero, the argument must be obtained from the
+ These are downcounted as float or non-float arguments are used,
+ and when they get to zero, the argument must be obtained from the
overflow region.
If TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT, then no FPR save area exists,
and a single pointer is enough. It's started at the GPR save area,
if (!TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
{
- tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
- tree ovfl, gtop, ftop, goff, foff;
+ tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
+ tree ovfl, gtop, ftop, goff, foff;
tree gprv;
int float_formals, fpr_offset, size_excess, floats_passed_in_regs;
int fpr_save_offset;
8 byte boundary. This means that the above calculation should
take into account the exact sequence of floats and non-floats
which make up the excess. That calculation should be rolled
- into the code which sets the current_function_args_info struct.
+ into the code which sets the current_function_args_info struct.
The above then reduces to a fetch from that struct. */
fpr_save_offset += 4;
}
if (fpr_save_offset)
- gprv = build (PLUS_EXPR, TREE_TYPE (ftop), gprv,
+ gprv = build (PLUS_EXPR, TREE_TYPE (ftop), gprv,
build_int_2 (-fpr_save_offset,-1));
t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, gprv);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
{
int indirect;
rtx r, lab_over = NULL_RTX, lab_false;
- tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
- tree ovfl, gtop, ftop, goff, foff;
+ tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
+ tree ovfl, gtop, ftop, goff, foff;
indirect
= function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
{
t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
build_int_2 (2*UNITS_PER_WORD - 1, 0));
- t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
+ t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
build_int_2 (-2*UNITS_PER_WORD, -1));
t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
}
- t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
+ t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
size_int (rsize));
r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
if (r != addr_rtx)
if (r != addr_rtx)
emit_move_insn (addr_rtx, r);
- /* Emit code for foff-=8.
+ /* Emit code for foff-=8.
Advances the offset up FPR save area by one double */
t = build (MINUS_EXPR, TREE_TYPE (foff), foff, build_int_2 (8, 0));
t = build (MODIFY_EXPR, TREE_TYPE (foff), foff, t);
emit_jump (lab_over);
emit_barrier ();
emit_label (lab_false);
-
- if (!TARGET_64BIT)
+
+ if (!TARGET_64BIT)
{
/* For mips2, the overflow area contains mixed size items.
If a 4-byte int is followed by an 8-byte float, then
/* Emit code for addr_rtx = the ovfl pointer into overflow area.
Regardless of mips2, postincrement the ovfl pointer by 8. */
- t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
+ t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
size_int (8));
r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
if (r != addr_rtx)
&& TREE_CODE (type) == INTEGER_TYPE
&& TYPE_PRECISION (type) == 64)
{
- /* In mips2, int takes 32 bits of the GPR save area, but
+ /* In mips2, int takes 32 bits of the GPR save area, but
longlong takes an aligned 64 bits. So, emit code
to zero the low order bits of goff, thus aligning
the later calculation of (gtop-goff) upwards. */
/* Emit code for goff = goff - step_size.
Advances the offset up GPR save area over the item. */
- t = build (MINUS_EXPR, TREE_TYPE (goff), goff,
+ t = build (MINUS_EXPR, TREE_TYPE (goff), goff,
build_int_2 (step_size, 0));
t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
emit_jump (lab_over);
emit_barrier ();
emit_label (lab_false);
-
+
/* Emit code for addr_rtx -> overflow area, postinc by step_size */
- t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
+ t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
size_int (step_size));
r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
if (r != addr_rtx)
/* Not EABI. */
int align;
- /* ??? The original va-mips.h did always align, despite the fact
+ /* ??? The original va-mips.h did always align, despite the fact
that alignments <= UNITS_PER_WORD are preserved by the va_arg
increment mechanism. */
align = 8;
else
align = 4;
-
+
t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
build_int_2 (align - 1, 0));
t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
/* If both single-float and soft-float are set, then clear the one that
was set by TARGET_DEFAULT, leaving the one that was set by the
- user. We assume here that the specs prevent both being set by the
+ user. We assume here that the specs prevent both being set by the
user. */
#ifdef TARGET_DEFAULT
if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
if (mips_isa_string == 0)
mips_isa = MIPS_ISA_DEFAULT;
+ else if (mips_isa_string != 0
+ && mips_arch_string != 0)
+ warning ("The -march option is incompatible to -mipsN and therefore ignored.");
+
else if (ISDIGIT (*mips_isa_string))
{
mips_isa = atoi (mips_isa_string);
error ("bad value (%s) for -mabi= switch", mips_abi_string);
/* A specified ISA defaults the ABI if it was not specified. */
- if (mips_abi_string == 0 && mips_isa_string
+ if (mips_abi_string == 0 && mips_isa_string
&& mips_abi != ABI_EABI && mips_abi != ABI_O64)
{
if (! ISA_HAS_64BIT_REGS)
}
/* A specified ABI defaults the ISA if it was not specified. */
- else if (mips_isa_string == 0 && mips_abi_string
+ else if (mips_isa_string == 0 && mips_abi_string
&& mips_abi != ABI_EABI && mips_abi != ABI_O64)
{
if (mips_abi == ABI_32)
greater than that supported by the default processor, then the user gets
an error. Normally, the compiler will just default to the base level cpu
for the indicated isa. */
- if (mips_cpu_string == 0)
- mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
+ if (mips_arch_string == 0)
+ mips_arch_string = MIPS_CPU_STRING_DEFAULT;
+ if (mips_tune_string == 0)
+ mips_tune_string = MIPS_CPU_STRING_DEFAULT;
#endif
/* Identify the processor type. */
- if (mips_cpu_string == 0
- || ! strcmp (mips_cpu_string, "default")
- || ! strcmp (mips_cpu_string, "DEFAULT"))
+ if (mips_cpu_string != 0)
{
- switch (mips_isa)
+ int mips_cpu = mips_parse_cpu (mips_cpu_string);
+
+ if (mips_cpu == PROCESSOR_DEFAULT)
{
- default:
- mips_cpu_string = "3000";
- mips_cpu = PROCESSOR_R3000;
- break;
- case 2:
- mips_cpu_string = "6000";
- mips_cpu = PROCESSOR_R6000;
- break;
- case 3:
- mips_cpu_string = "4000";
- mips_cpu = PROCESSOR_R4000;
- break;
- case 4:
- mips_cpu_string = "8000";
- mips_cpu = PROCESSOR_R8000;
- break;
+ error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
+ mips_cpu_string = "default";
}
+ mips_arch = mips_cpu;
+ mips_tune = mips_cpu;
}
- else
- {
- const char *p = mips_cpu_string;
- int seen_v = 0;
-
- /* We need to cope with the various "vr" prefixes for the NEC 4300
- and 4100 processors. */
- if (*p == 'v' || *p == 'V')
- seen_v = 1, p++;
- if (*p == 'r' || *p == 'R')
- p++;
-
- /* Since there is no difference between a R2000 and R3000 in
- terms of the scheduler, we collapse them into just an R3000. */
-
- mips_cpu = PROCESSOR_DEFAULT;
- switch (*p)
- {
- case '2':
- if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
- mips_cpu = PROCESSOR_R3000;
- break;
-
- case '3':
- if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
- mips_cpu = PROCESSOR_R3000;
- else if (!strcmp (p, "3900"))
- mips_cpu = PROCESSOR_R3900;
- break;
-
- case '4':
- if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
- mips_cpu = PROCESSOR_R4000;
- /* The vr4100 is a non-FP ISA III processor with some extra
- instructions. */
- else if (!strcmp (p, "4100"))
- {
- mips_cpu = PROCESSOR_R4100;
- target_flags |= MASK_SOFT_FLOAT ;
- }
- /* The vr4300 is a standard ISA III processor, but with a different
- pipeline. */
- else if (!strcmp (p, "4300"))
- mips_cpu = PROCESSOR_R4300;
- /* The r4400 is exactly the same as the r4000 from the compiler's
- viewpoint. */
- else if (!strcmp (p, "4400"))
- mips_cpu = PROCESSOR_R4000;
- else if (!strcmp (p, "4600"))
- mips_cpu = PROCESSOR_R4600;
- else if (!strcmp (p, "4650"))
- mips_cpu = PROCESSOR_R4650;
- break;
-
- case '5':
- if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
- mips_cpu = PROCESSOR_R5000;
- break;
-
- case '6':
- if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
- mips_cpu = PROCESSOR_R6000;
- break;
-
- case '8':
- if (!strcmp (p, "8000"))
- mips_cpu = PROCESSOR_R8000;
- break;
-
- case 'o':
- if (!strcmp (p, "orion"))
- mips_cpu = PROCESSOR_R4600;
- break;
+ if (mips_arch_string == 0
+ || ! strcmp (mips_arch_string, "default")
+ || ! strcmp (mips_arch_string, "DEFAULT"))
+ {
+ switch (mips_isa)
+ {
+ default:
+ mips_arch_string = "3000";
+ mips_arch = PROCESSOR_R3000;
+ break;
+ case 2:
+ mips_arch_string = "6000";
+ mips_arch = PROCESSOR_R6000;
+ break;
+ case 3:
+ mips_arch_string = "4000";
+ mips_arch = PROCESSOR_R4000;
+ break;
+ case 4:
+ mips_arch_string = "8000";
+ mips_arch = PROCESSOR_R8000;
+ break;
}
+ }
+ else
+ {
+ mips_arch = mips_parse_cpu (mips_arch_string);
- if (seen_v
- && mips_cpu != PROCESSOR_R4300
- && mips_cpu != PROCESSOR_R4100
- && mips_cpu != PROCESSOR_R5000)
- mips_cpu = PROCESSOR_DEFAULT;
+ if (mips_arch == PROCESSOR_DEFAULT)
+ {
+ error ("bad value (%s) for -march= switch", mips_arch_string);
+ mips_arch_string = "default";
+ }
+ }
+ if (mips_tune_string == 0
+ || ! strcmp (mips_tune_string, "default")
+ || ! strcmp (mips_tune_string, "DEFAULT"))
+ {
+ if (mips_arch != PROCESSOR_DEFAULT)
+ mips_tune = mips_arch;
+ else
+ switch (mips_isa)
+ {
+ default:
+ mips_tune_string = "3000";
+ mips_tune = PROCESSOR_R3000;
+ break;
+ case 2:
+ mips_tune_string = "6000";
+ mips_tune = PROCESSOR_R6000;
+ break;
+ case 3:
+ mips_tune_string = "4000";
+ mips_tune = PROCESSOR_R4000;
+ break;
+ case 4:
+ mips_tune_string = "8000";
+ mips_tune = PROCESSOR_R8000;
+ break;
+ }
- if (mips_cpu == PROCESSOR_DEFAULT)
- {
- error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
- mips_cpu_string = "default";
- }
+ }
+ else
+ {
+ mips_tune = mips_parse_cpu (mips_tune_string);
+ if (mips_tune == PROCESSOR_DEFAULT)
+ {
+ error ("bad value (%s) for -mtune= switch", mips_tune_string);
+ mips_tune_string = "default";
+ }
}
- if ((mips_cpu == PROCESSOR_R3000 && (mips_isa != 1))
- || (mips_cpu == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
- || ((mips_cpu == PROCESSOR_R4000
- || mips_cpu == PROCESSOR_R4100
- || mips_cpu == PROCESSOR_R4300
- || mips_cpu == PROCESSOR_R4600
- || mips_cpu == PROCESSOR_R4650)
- && mips_isa != 1 && mips_isa != 2 && mips_isa != 3))
- error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
/* make sure sizes of ints/longs/etc. are ok */
if (! ISA_HAS_64BIT_REGS)
/* Provide default values for align_* for 64-bit targets. */
if (TARGET_64BIT && !TARGET_MIPS16)
{
- if (align_loops == 0)
+ if (align_loops == 0)
align_loops = 8;
- if (align_jumps == 0)
+ if (align_jumps == 0)
align_jumps = 8;
- if (align_functions == 0)
+ if (align_functions == 0)
align_functions = 8;
}
fputs (".set\tnoat\n\t", file);
break;
- case ']':
+ case ']':
if (set_noat == 0)
error ("internal error: %%] found without a %%[ in assembler pattern");
else if (--set_noat == 0)
fprintf (stream, "\n\t%s.loc\t%d %d\n",
(ignore_line_number) ? "#" : "",
num_source_filenames, line);
-
+
LABEL_AFTER_LOC (stream);
}
}
asm_out_data_file = asm_out_text_file = stream;
if (flag_verbose_asm)
- fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
+ fprintf (stream, "\n%s -G value = %d, Apu = %s, ISA = %d\n",
ASM_COMMENT_START,
- mips_section_threshold, mips_cpu_string, mips_isa);
+ mips_section_threshold, mips_arch_string, mips_isa);
}
\f
/* If we are optimizing the global pointer, emit the text section now and any
}
}
}
-
+
if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
{
fprintf (file, "\n\t.text\n");
The gp reg is callee saved in the 64 bit ABI, so all routines must
save the gp reg. This is not a leaf routine if -p, because of the
call to mcount. */
- if (total_size == extra_size
+ if (total_size == extra_size
&& (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
&& ! profile_flag)
total_size = extra_size = 0;
insn = emit_move_insn (mem_rtx, reg_rtx);
RTX_FRAME_RELATED_P (insn) = 1;
}
- else
+ else
{
emit_move_insn (reg_rtx, mem_rtx);
if (TARGET_MIPS16
? (store_p) ? "sd" : "ld"
: (store_p) ? "sw" : "lw"),
reg_names[r]);
- fprintf (file, HOST_WIDE_INT_PRINT_DEC,
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC,
gp_offset - base_offset);
fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
if (! store_p
/* For arguments passed in registers, find the register number
of the first argument in the variable part of the argument list,
- otherwise GP_ARG_LAST+1. Note also if the last argument is
+ otherwise GP_ARG_LAST+1. Note also if the last argument is
the varargs special argument, and treat it as part of the
variable arguments.
-
+
This is only needed if store_args_on_stack is true. */
INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
g6_rtx));
tsize = 0;
}
-
+
if (tsize && tsize != orig_tsize)
tsize_rtx = GEN_INT (tsize);
}
if (GET_CODE (x) == CONST)
return symbolic_expression_p (XEXP (x, 0));
-
+
if (GET_RTX_CLASS (GET_CODE (x)) == '1')
return symbolic_expression_p (XEXP (x, 0));
{
/* For hosted applications, always put constants in small data if
possible, as this gives the best performance. */
-
+
if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
&& mips_section_threshold > 0)
SMALL_DATA_SECTION ();
}
else if (TREE_CODE (valtype) == RECORD_TYPE
- && mips_abi != ABI_32
- && mips_abi != ABI_O64
+ && mips_abi != ABI_32
+ && mips_abi != ABI_O64
&& mips_abi != ABI_EABI)
{
/* A struct with only one or two floating point fields is returned in
fields[i++] = field;
}
-
+
/* Must check i, so that we reject structures with no elements. */
if (! field)
{
here hopefully is not relevant to mips_va_arg. */
if (cum && MUST_PASS_IN_STACK (mode, type))
{
- /* Don't pass the actual CUM to FUNCTION_ARG, because we would
- get double copies of any offsets generated for small structs
+ /* Don't pass the actual CUM to FUNCTION_ARG, because we would
+ get double copies of any offsets generated for small structs
passed in registers. */
CUMULATIVE_ARGS temp;
temp = *cum;
&& strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
return 0;
- /* This code will only work for o32 and o64 abis. The other ABI's
+ /* This code will only work for o32 and o64 abis. The other ABI's
require more sophisticated support. */
if (mips_abi != ABI_32 && mips_abi != ABI_O64)
abort ();
emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
force_const_mem (Pmode, sym)),
next);
-
+
PUT_CODE (insn, NOTE);
NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
NOTE_SOURCE_FILE (insn) = 0;
constants = NULL;
first_constant_ref = -1;
}
-
+
if (constants != NULL
- && (NEXT_INSN (insn) == NULL
- || (first_constant_ref >= 0
+ && (NEXT_INSN (insn) == NULL
+ || (first_constant_ref >= 0
&& (((addr - first_constant_ref)
+ 2 /* for alignment */
+ 2 /* for a short jump insn */
emit a barrier now. */
rtx label, jump, barrier;
-
+
label = gen_label_rtx ();
jump = emit_jump_insn_after (gen_jump (label), insn);
JUMP_LABEL (jump) = label;
|| code == ROTATE);
}
-/* Return the length of INSN. LENGTH is the initial length computed by
+/* Return the length of INSN. LENGTH is the initial length computed by
attributes in the machine-description file. */
int
of a sequence. A conditional jump normally has a delay slot, but
does not on MIPS16. */
if (simplejump_p (insn)
- || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
+ || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
|| GET_CODE (insn) == CALL_INSN)))
length += 4;
return length;
}
-/* Output assembly instructions to peform a conditional branch.
+/* Output assembly instructions to peform a conditional branch.
INSN is the branch instruction. OPERANDS[0] is the condition.
OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
That tells us whether to generate a simple conditional branch, or a
reversed conditional branch around a `jr' instruction. */
char *
-mips_output_conditional_branch (insn,
- operands,
+mips_output_conditional_branch (insn,
+ operands,
two_operands_p,
float_p,
inverted_p,
equality comparisons are done between two operands, and therefore
do not require a `z' in the assembly language output. */
need_z_p = (!float_p && code != EQ && code != NE);
- /* For comparisons against zero, the zero is not provided
+ /* For comparisons against zero, the zero is not provided
explicitly. */
if (need_z_p)
op2 = "";
strcat to add to it. */
buffer[0] = '\0';
- switch (length)
+ switch (length)
{
case 4:
case 8:
generate only a four-byte sequence, rather than eight, and
there seems to be no way to tell it not to. Thus, we can't
just use a `.+x' addressing form; we don't know what value
- to give for `x'.
+ to give for `x'.
So, we resort to using the explicit relocation syntax
available in the assembler and do:
anything. */
/* The target of the reversed branch. */
- const char *target
+ const char *target
= ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
strcpy (buffer, "%(%<%[");
c = strchr (buffer, '\0');
- /* Generate the reversed comparision. This takes four
+ /* Generate the reversed comparision. This takes four
bytes. */
if (float_p)
sprintf (c, "%%*b%s\t%%Z2%s",
ggc_add_rtx_root (&embedded_pic_fnaddr_rtx, 1);
ggc_add_rtx_root (&mips16_gp_pseudo_rtx, 1);
}
+
+static enum processor_type
+mips_parse_cpu (cpu_string)
+ const char *cpu_string;
+{
+ const char *p = cpu_string;
+ int seen_v = 0;
+ enum processor_type cpu;
+
+ /* We need to cope with the various "vr" prefixes for the NEC 4300
+ and 4100 processors. */
+ if (*p == 'v' || *p == 'V')
+ seen_v = 1, p++;
+
+ if (*p == 'r' || *p == 'R')
+ p++;
+
+ /* Since there is no difference between a R2000 and R3000 in
+ terms of the scheduler, we collapse them into just an R3000. */
+
+ cpu = PROCESSOR_DEFAULT;
+ switch (*p)
+ {
+ case '2':
+ if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
+ cpu = PROCESSOR_R3000;
+ break;
+
+ case '3':
+ if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
+ cpu = PROCESSOR_R3000;
+ else if (!strcmp (p, "3900"))
+ cpu = PROCESSOR_R3900;
+ break;
+
+ case '4':
+ if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
+ cpu = PROCESSOR_R4000;
+ /* The vr4100 is a non-FP ISA III processor with some extra
+ instructions. */
+ else if (!strcmp (p, "4100"))
+ cpu = PROCESSOR_R4100;
+ /* The vr4300 is a standard ISA III processor, but with a different
+ pipeline. */
+ else if (!strcmp (p, "4300"))
+ cpu = PROCESSOR_R4300;
+ /* The r4400 is exactly the same as the r4000 from the compiler's
+ viewpoint. */
+ else if (!strcmp (p, "4400"))
+ cpu = PROCESSOR_R4000;
+ else if (!strcmp (p, "4600"))
+ cpu = PROCESSOR_R4600;
+ else if (!strcmp (p, "4650"))
+ cpu = PROCESSOR_R4650;
+
+ case '5':
+ if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
+ cpu = PROCESSOR_R5000;
+ break;
+
+ case '6':
+ if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
+ cpu = PROCESSOR_R6000;
+ break;
+
+ case '8':
+ if (!strcmp (p, "8000"))
+ cpu = PROCESSOR_R8000;
+ break;
+
+ case 'o':
+ if (!strcmp (p, "orion"))
+ cpu = PROCESSOR_R4600;
+ break;
+ }
+
+ if (seen_v
+ && cpu != PROCESSOR_R4300
+ && cpu != PROCESSOR_R4100
+ && cpu != PROCESSOR_R5000)
+ cpu = PROCESSOR_DEFAULT;
+
+ return cpu;
+}
/* Definitions of target machine for GNU compiler. MIPS version.
Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
- 1999, 2000, 2001 Free Software Foundation, Inc.
+ 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
Contributed by A. Lichnewsky (lich@inria.inria.fr).
Changed by Michael Meissner (meissner@osf.org).
64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
};
/* Recast the cpu class to be the cpu attribute. */
-#define mips_cpu_attr ((enum attr_cpu)mips_cpu)
+#define mips_cpu_attr ((enum attr_cpu)mips_tune)
/* Which ABI to use. These are constants because abi64.h must check their
value at preprocessing time.
extern int mips_dbx_regno[]; /* Map register # to debug register # */
extern struct rtx_def *branch_cmp[2]; /* operands for compare */
extern enum cmp_type branch_type; /* what type of branch to use */
-extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
+extern enum processor_type mips_arch; /* which cpu to codegen for */
+extern enum processor_type mips_tune; /* which cpu to schedule for */
extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
extern int mips_isa; /* architectural level */
extern int mips16; /* whether generating mips16 code */
extern int mips16_hard_float; /* mips16 without -msoft-float */
extern int mips_entry; /* generate entry/exit for mips16 */
extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
+extern const char *mips_arch_string; /* for -march=<xxx> */
+extern const char *mips_tune_string; /* for -mtune=<xxx> */
extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
extern const char *mips_entry_string; /* for -mentry */
| TARGET_CPU_DEFAULT \
| TARGET_ENDIAN_DEFAULT), \
NULL}, \
-}
+}
/* Default target_flags if no switches are specified */
initializer with a subgrouping for each command option.
Each subgrouping contains a string constant, that defines the
- fixed part of the option name, and the address of a variable.
+ fixed part of the option name, and the address of a variable.
The variable, type `char *', is set to the variable part of the
given option if the fixed part matches. The actual option name
is made by appending `-m' to the specified name.
SUBTARGET_TARGET_OPTIONS \
{ "cpu=", &mips_cpu_string, \
N_("Specify CPU for scheduling purposes")}, \
+ { "tune=", &mips_tune_string, \
+ N_("Specify CPU for scheduling purposes")}, \
+ { "arch=", &mips_arch_string, \
+ N_("Specify CPU for code generation purposes")}, \
{ "ips", &mips_isa_string, \
N_("Specify MIPS ISA")}, \
{ "entry", &mips_entry_string, \
#define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
)
-/* ISA has branch likely instructions (eg. mips2). */
+/* ISA has branch likely instructions (eg. mips2). */
#define ISA_HAS_BRANCHLIKELY (mips_isa != 1)
/* ISA has the conditional move instructions introduced in mips4. */
/* This is a catch all for the other new mips4 instructions: indexed load and
- indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
+ indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
and the FP recip and recip sqrt instructions */
#define ISA_HAS_FP4 (mips_isa == 4 \
)
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
- done, NIL if none.
+ done, NIL if none.
When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
moves. All other referces are zero extended. */
? SIGN_EXTEND : ZERO_EXTEND)
/* Define this macro if it is advisable to hold scalars in registers
- in a wider mode than that declared by the program. In such cases,
+ in a wider mode than that declared by the program. In such cases,
the value is constrained to be within the bounds of the declared
type, but kept valid in the wider mode. The signedness of the
extension may differ from that of the type.
/* The register number of the register used to address a table of
static data addresses in memory. In some cases this register is
- defined by a processor's "application binary interface" (ABI).
+ defined by a processor's "application binary interface" (ABI).
When this macro is defined, RTL is generated for this register
once, as with the stack pointer and frame pointer registers. If
this macro is not defined, it is up to the machine-dependent
&& (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
/* Letters in the range `Q' through `U' may be defined in a
- machine-dependent fashion to stand for arbitrary operand types.
+ machine-dependent fashion to stand for arbitrary operand types.
The machine description macro `EXTRA_CONSTRAINT' is passed the
operand as its first argument and the constraint letter as its
second operand.
On some machines, the position of the argument pointer is not
known until the compilation is completed. In such a case, a
- separate hard register must be used for the argument pointer.
+ separate hard register must be used for the argument pointer.
This register can be eliminated by replacing it with either the
frame pointer or the argument pointer, depending on whether or not
the frame pointer has been eliminated.
((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
/* Define this if it is the responsibility of the caller to
- allocate the area reserved for arguments passed in registers.
+ allocate the area reserved for arguments passed in registers.
If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
- of this macro is to determine whether the space is included in
+ of this macro is to determine whether the space is included in
`current_function_outgoing_args_size'. */
#define OUTGOING_REG_PARM_STACK_SPACE
int fp_code; /* Mode of FP arguments (mips16) */
unsigned int num_adjusts; /* number of adjustments made */
/* Adjustments made to args pass in regs. */
- /* ??? The size is doubled to work around a
+ /* ??? The size is doubled to work around a
bug in the code that sets the adjustments
in function_arg. */
struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
\f
/* A C statement to output, on the stream FILE, assembler code for a
- block of data that contains the constant parts of a trampoline.
+ block of data that contains the constant parts of a trampoline.
This code should not include a label--the label is taken care of
automatically. */
#define CACHE_FLUSH_FUNC "_flush_cache"
#endif
-/* A C statement to initialize the variable parts of a trampoline.
+/* A C statement to initialize the variable parts of a trampoline.
ADDR is an RTX for the address of the trampoline; FNADDR is an
RTX for the address of the nested function; STATIC_CHAIN is an
RTX for the static chain value that should be passed to the
to understand.
This macro must exist in two variants: a strict variant and a
- non-strict one. The strict variant is used in the reload pass.
+ non-strict one. The strict variant is used in the reload pass.
It must be defined so that any pseudo-register that has not been
allocated a hard register is considered a memory reference. In
contexts where some kind of register is required, a
On some machines, whether a symbolic address is legitimate
depends on the section that the address refers to. On these
machines, define the macro `ENCODE_SECTION_INFO' to store the
- information into the `symbol_ref', and then check for it here.
+ information into the `symbol_ref', and then check for it here.
When you see a `const', you will have to look inside it to find
the `symbol_ref' in order to determine the section. */
to be generated at present. Also, the MIPS assembler does not
grok li.d Infinity. */
-/* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
+/* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
Note that the Irix 6 assembler problem may already be fixed.
Note also that the GET_CODE (X) == CONST test catches the mips16
gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
When PIC, convert addresses of the form memory (symbol+large int) to
memory (reg+large int). */
-
+
#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
{ \
function named by the symbol (such as what section it is in).
The macro definition, if any, is executed immediately after the
- rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
+ rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
The value of the rtl will be a `mem' whose address is a
`symbol_ref'.
information).
The best way to modify the name string is by adding text to the
- beginning, with suitable punctuation to prevent any ambiguity.
+ beginning, with suitable punctuation to prevent any ambiguity.
Allocate the new name in `saveable_obstack'. You will have to
modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
and output the name accordingly.
constants which are put in the .text section. We also record the
total length of all such strings; this total is used to decide
whether we need to split the constant table, and need not be
- precisely correct.
+ precisely correct.
When not mips16 code nor embedded PIC, if a symbol is in a
gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
enum machine_mode xmode = GET_MODE (X); \
if (xmode == SFmode || xmode == DFmode) \
{ \
- if (mips_cpu == PROCESSOR_R3000 \
- || mips_cpu == PROCESSOR_R3900) \
+ if (mips_tune == PROCESSOR_R3000 \
+ || mips_tune == PROCESSOR_R3900) \
return COSTS_N_INSNS (2); \
- else if (mips_cpu == PROCESSOR_R6000) \
+ else if (mips_tune == PROCESSOR_R6000) \
return COSTS_N_INSNS (3); \
else \
return COSTS_N_INSNS (6); \
enum machine_mode xmode = GET_MODE (X); \
if (xmode == SFmode) \
{ \
- if (mips_cpu == PROCESSOR_R3000 \
- || mips_cpu == PROCESSOR_R3900 \
- || mips_cpu == PROCESSOR_R5000) \
+ if (mips_tune == PROCESSOR_R3000 \
+ || mips_tune == PROCESSOR_R3900 \
+ || mips_tune == PROCESSOR_R5000) \
return COSTS_N_INSNS (4); \
- else if (mips_cpu == PROCESSOR_R6000) \
+ else if (mips_tune == PROCESSOR_R6000) \
return COSTS_N_INSNS (5); \
else \
return COSTS_N_INSNS (7); \
\
if (xmode == DFmode) \
{ \
- if (mips_cpu == PROCESSOR_R3000 \
- || mips_cpu == PROCESSOR_R3900 \
- || mips_cpu == PROCESSOR_R5000) \
+ if (mips_tune == PROCESSOR_R3000 \
+ || mips_tune == PROCESSOR_R3900 \
+ || mips_tune == PROCESSOR_R5000) \
return COSTS_N_INSNS (5); \
- else if (mips_cpu == PROCESSOR_R6000) \
+ else if (mips_tune == PROCESSOR_R6000) \
return COSTS_N_INSNS (6); \
else \
return COSTS_N_INSNS (8); \
} \
\
- if (mips_cpu == PROCESSOR_R3000) \
+ if (mips_tune == PROCESSOR_R3000) \
return COSTS_N_INSNS (12); \
- else if (mips_cpu == PROCESSOR_R3900) \
+ else if (mips_tune == PROCESSOR_R3900) \
return COSTS_N_INSNS (2); \
- else if (mips_cpu == PROCESSOR_R6000) \
+ else if (mips_tune == PROCESSOR_R6000) \
return COSTS_N_INSNS (17); \
- else if (mips_cpu == PROCESSOR_R5000) \
+ else if (mips_tune == PROCESSOR_R5000) \
return COSTS_N_INSNS (5); \
else \
return COSTS_N_INSNS (10); \
enum machine_mode xmode = GET_MODE (X); \
if (xmode == SFmode) \
{ \
- if (mips_cpu == PROCESSOR_R3000 \
- || mips_cpu == PROCESSOR_R3900) \
+ if (mips_tune == PROCESSOR_R3000 \
+ || mips_tune == PROCESSOR_R3900) \
return COSTS_N_INSNS (12); \
- else if (mips_cpu == PROCESSOR_R6000) \
+ else if (mips_tune == PROCESSOR_R6000) \
return COSTS_N_INSNS (15); \
else \
return COSTS_N_INSNS (23); \
\
if (xmode == DFmode) \
{ \
- if (mips_cpu == PROCESSOR_R3000 \
- || mips_cpu == PROCESSOR_R3900) \
+ if (mips_tune == PROCESSOR_R3000 \
+ || mips_tune == PROCESSOR_R3900) \
return COSTS_N_INSNS (19); \
- else if (mips_cpu == PROCESSOR_R6000) \
+ else if (mips_tune == PROCESSOR_R6000) \
return COSTS_N_INSNS (16); \
else \
return COSTS_N_INSNS (36); \
\
case UDIV: \
case UMOD: \
- if (mips_cpu == PROCESSOR_R3000 \
- || mips_cpu == PROCESSOR_R3900) \
+ if (mips_tune == PROCESSOR_R3000 \
+ || mips_tune == PROCESSOR_R3900) \
return COSTS_N_INSNS (35); \
- else if (mips_cpu == PROCESSOR_R6000) \
+ else if (mips_tune == PROCESSOR_R6000) \
return COSTS_N_INSNS (38); \
- else if (mips_cpu == PROCESSOR_R5000) \
+ else if (mips_tune == PROCESSOR_R5000) \
return COSTS_N_INSNS (36); \
else \
return COSTS_N_INSNS (69); \
used.
For example, suppose an address that is equal to the sum of a
- register and a constant is used twice in the same basic block.
+ register and a constant is used twice in the same basic block.
When this macro is not defined, the address will be computed in
a register and memory references will be indirect through that
register. On machines where the cost of the addressing mode
defining `ADDRESS_COST' to reflect this can cause two registers
to be live over a region of code where only one would have been
if `ADDRESS_COST' were not defined in that manner. This effect
- should be considered in the definition of this macro.
+ should be considered in the definition of this macro.
Equivalent costs should probably only be given to addresses with
different numbers of registers on machines with lots of registers.
/* ??? Fix this to be right for the R8000. */
#define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
- (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
+ (((mips_tune == PROCESSOR_R4000 || mips_tune == PROCESSOR_R6000) ? 6 : 4) \
+ memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
/* Define if copies to/from condition code registers should be avoided.
/* ??? Fix this to be right for the R8000. */
#define BRANCH_COST \
((! TARGET_MIPS16 \
- && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
+ && (mips_tune == PROCESSOR_R4000 || mips_tune == PROCESSOR_R6000)) \
? 2 : 1)
/* A C statement (sans semicolon) to update the integer variable COST
Defining this macro does not affect the generated code (however,
incorrect definitions that omit an rtl code that may be matched
- by the predicate can cause the compiler to malfunction).
+ by the predicate can cause the compiler to malfunction).
Instead, it allows the table built by `genrecog' to be more
compact and efficient, thus speeding up the compiler. The most
important predicates to include in the list specified by this
/* A C statement (sans semicolon) to output to the stdio stream
STREAM any text necessary for declaring the name NAME of an
initialized variable which is being defined. This macro must
- output the label definition (perhaps using `ASM_OUTPUT_LABEL').
+ output the label definition (perhaps using `ASM_OUTPUT_LABEL').
The argument DECL is the `VAR_DECL' tree node representing the
variable.
fprintf (STREAM, "\n"); \
} while (0)
-/* Likewise for 64 bit, `char' and `short' constants.
+/* Likewise for 64 bit, `char' and `short' constants.
FIXME: operand_subword can't handle some complex constant expressions
that output_addr_const can (for example it does not call
- simplify_subtraction). Since GAS can handle dword, even for mipsII,
+ simplify_subtraction). Since GAS can handle dword, even for mipsII,
rely on that to avoid operand_subword for most of the cases where this
matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
or the same case with the type of 'i' changed to long long.
;; instruction which allows full access to the entire address space,
;; but we do not do so at present.
-(define_attr "length" ""
+(define_attr "length" ""
(cond [(eq_attr "type" "branch")
(cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
(const_int 131072))
;; Attribute describing the processor
;; (define_attr "cpu" "default,r3000,r6000,r4000"
;; (const
-;; (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000")) (const_string "r3000")
-;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000")) (const_string "r4000")
-;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000")) (const_string "r6000")]
+;; (cond [(eq (symbol_ref "mips_tune") (symbol_ref "PROCESSOR_R3000")) (const_string "r3000")
+;; (eq (symbol_ref "mips_tune") (symbol_ref "PROCESSOR_R4000")) (const_string "r4000")
+;; (eq (symbol_ref "mips_tune") (symbol_ref "PROCESSOR_R6000")) (const_string "r6000")]
;; (const_string "default"))))
;; ??? Fix everything that tests this attribute.
;; Does the instruction have a mandatory delay slot?
;; The 3900, is (mostly) mips1, but does not have a mandatory load delay
-;; slot.
+;; slot.
(define_attr "dslot" "no,yes"
(if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp")
(and (eq_attr "type" "load")
;; (define_function_unit "memory" 1 0 (eq_attr "type" "load") 3 0)
;; (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
-;;
+;;
;; (define_function_unit "fp_comp" 1 0 (eq_attr "type" "fcmp") 2 0)
-;;
+;;
;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer") 2 0)
;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo") 3 0)
-;;
+;;
;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "imul") 17 0)
;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "idiv") 38 0)
-;;
+;;
;; (define_function_unit "adder" 1 1 (eq_attr "type" "fadd") 4 0)
;; (define_function_unit "adder" 1 1 (eq_attr "type" "fabs,fneg") 2 0)
-;;
+;;
;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF")) 7 0)
;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF")) 8 0)
-;;
+;;
;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF")) 23 0)
;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF")) 36 0)
-;;
+;;
;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0)
;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0)
\f
(const_int 4)
(const_int 8))
(const_int 4)])])
-
+
\f
;;
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"
{
- if (mips_cpu != PROCESSOR_R4300)
+ if (mips_arch != PROCESSOR_R4300)
emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
else
emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu != PROCESSOR_R4300"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_arch != PROCESSOR_R4300"
"mul.d\\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "DF")])
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu == PROCESSOR_R4300"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_arch == PROCESSOR_R4300"
"*
{
output_asm_insn (\"mul.d\\t%0,%1,%2\", operands);
"TARGET_HARD_FLOAT"
"
{
- if (mips_cpu != PROCESSOR_R4300)
+ if (mips_arch != PROCESSOR_R4300)
emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
else
emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
[(set (match_operand:SF 0 "register_operand" "=f")
(mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && mips_cpu != PROCESSOR_R4300"
+ "TARGET_HARD_FLOAT && mips_arch != PROCESSOR_R4300"
"mul.s\\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "SF")])
[(set (match_operand:SF 0 "register_operand" "=f")
(mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && mips_cpu == PROCESSOR_R4300"
+ "TARGET_HARD_FLOAT && mips_arch == PROCESSOR_R4300"
"*
{
output_asm_insn (\"mul.s\\t%0,%1,%2\", operands);
{
if (HAVE_mulsi3_mult3)
emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
- else if (mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16)
+ else if (mips_arch != PROCESSOR_R4000 || TARGET_MIPS16)
emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
else
emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_scratch:SI 3 "=h"))
(clobber (match_scratch:SI 4 "=a"))]
- "mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16"
+ "mips_arch != PROCESSOR_R4000 || TARGET_MIPS16"
"mult\\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
(clobber (match_scratch:SI 3 "=h"))
(clobber (match_scratch:SI 4 "=l"))
(clobber (match_scratch:SI 5 "=a"))]
- "mips_cpu == PROCESSOR_R4000 && !TARGET_MIPS16"
+ "mips_arch == PROCESSOR_R4000 && !TARGET_MIPS16"
"*
{
rtx xoperands[10];
"
{
- if (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16)
+ if (GENERATE_MULT3 || mips_arch == PROCESSOR_R4000 || TARGET_MIPS16)
emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
else
emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
(match_operand:DI 2 "register_operand" "d")))
(clobber (match_scratch:DI 3 "=h"))
(clobber (match_scratch:DI 4 "=a"))]
- "TARGET_64BIT && mips_cpu != PROCESSOR_R4000 && !TARGET_MIPS16"
+ "TARGET_64BIT && mips_arch != PROCESSOR_R4000 && !TARGET_MIPS16"
"dmult\\t%1,%2"
[(set_attr "type" "imul")
(set_attr "mode" "DI")])
(clobber (match_scratch:DI 3 "=h"))
(clobber (match_scratch:DI 4 "=l"))
(clobber (match_scratch:DI 5 "=a"))]
- "TARGET_64BIT && (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000 || TARGET_MIPS16)"
+ "TARGET_64BIT && (GENERATE_MULT3 || mips_arch == PROCESSOR_R4000 || TARGET_MIPS16)"
"*
{
if (GENERATE_MULT3)
output_asm_insn (\"dmult\\t%0,%1,%2\", operands);
- else
+ else
{
rtx xoperands[10];
(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f"))
(match_operand:SF 3 "register_operand" "f")))]
-
+
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"msub.s\\t%0,%3,%1,%2"
[(set_attr "type" "fmadd")
copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
GEN_INT (0x6)));
}
-
+
DONE;
}")
copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
GEN_INT (0x6)));
}
-
+
DONE;
}")
GEN_INT (0),
GEN_INT (0x7)));
}
-
+
DONE;
}")
GEN_INT (0),
GEN_INT (0x7)));
}
-
+
DONE;
}")
have_dep_anti = 1;
if (! have_dep_anti)
{
- /* No branch delay slots on mips16. */
+ /* No branch delay slots on mips16. */
if (which_alternative == 1)
return \"%(bnez\\t%0,1f\\n\\tbreak\\t%2\\n%~1:%)\";
else
copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
GEN_INT (0x6)));
}
-
+
DONE;
}")
(define_expand "divdi3"
[(set (match_operand:DI 0 "register_operand" "=l")
(div:DI (match_operand:DI 1 "se_register_operand" "d")
- (match_operand:DI 2 "se_register_operand" "d")))
+ (match_operand:DI 2 "se_register_operand" "d")))
(clobber (match_scratch:DI 3 "=h"))
(clobber (match_scratch:DI 4 "=a"))]
"TARGET_64BIT && !optimize"
copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
GEN_INT (0x6)));
}
-
+
DONE;
}")
copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
GEN_INT (0x6)));
}
-
+
DONE;
}")
copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
GEN_INT (0x6)));
}
-
+
DONE;
}")
GEN_INT (0),
GEN_INT (0x7)));
}
-
+
DONE;
}")
GEN_INT (0),
GEN_INT (0x7)));
}
-
+
DONE;
}")
GEN_INT (0),
GEN_INT (0x7)));
}
-
+
DONE;
}")
GEN_INT (0),
GEN_INT (0x7)));
}
-
+
DONE;
}")
return \"%(bltzl\\t%1,1f\\n\\tsubu\\t%0,%z2,%0\\n%~1:%)\";
else
return \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n%~1:\";
- }
+ }
else
return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n%~1:%)\";
}"
dslots_jump_total++;
dslots_jump_filled++;
operands[2] = const0_rtx;
-
+
if (GET_CODE (operands[1]) == REG)
regno1 = REGNO (operands[1]);
- else
+ else
regno1 = REGNO (XEXP (operands[1], 0));
if (REGNO (operands[0]) == regno1)
{
if (TARGET_MIPS16)
return \"dsll\\t%0,%1,56\;dsra\\t%0,56\";
- return \"andi\\t%0,%1,0x00ff\";
+ return \"andi\\t%0,%1,0x00ff\";
}"
[(set_attr "type" "darith")
(set_attr "mode" "QI")
[(set_attr "type" "darith")
(set_attr "mode" "SI")
(set_attr "length" "8")])
-
+
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d")
(truncate:SI (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
"
{
/* If the field does not start on a byte boundary, then fail. */
- if (INTVAL (operands[3]) % 8 != 0)
+ if (INTVAL (operands[3]) % 8 != 0)
FAIL;
/* MIPS I and MIPS II can only handle a 32bit field. */
"
{
/* If the field does not start on a byte boundary, then fail. */
- if (INTVAL (operands[3]) % 8 != 0)
+ if (INTVAL (operands[3]) % 8 != 0)
FAIL;
/* MIPS I and MIPS II can only handle a 32bit field. */
"
{
/* If the field does not start on a byte boundary, then fail. */
- if (INTVAL (operands[2]) % 8 != 0)
+ if (INTVAL (operands[2]) % 8 != 0)
FAIL;
/* MIPS I and MIPS II can only handle a 32bit field. */
"
{
rtx scratch = gen_rtx_REG (DImode,
- (REGNO (operands[0]) == REGNO (operands[2])
+ (REGNO (operands[0]) == REGNO (operands[2])
? REGNO (operands[2]) + 1
: REGNO (operands[2])));
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_operand:SI 3 "register_operand" "=d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "*
+ "*
{
operands[4] = const0_rtx;
dslots_jump_total += 3;
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_operand:SI 3 "register_operand" "=d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "*
+ "*
{
operands[4] = const0_rtx;
dslots_jump_total += 3;
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_operand:SI 3 "register_operand" "=d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "*
+ "*
{
operands[4] = const0_rtx;
dslots_jump_total += 3;
(define_insn "branch_fp"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:CC 0 "cmp_op"
[(match_operand:CC 2 "register_operand" "z")
(const_int 0)])
(define_insn "branch_fp_inverted"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:CC 0 "cmp_op"
[(match_operand:CC 2 "register_operand" "z")
(const_int 0)])
(define_insn "branch_zero"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:SI 0 "cmp_op"
[(match_operand:SI 2 "register_operand" "d")
(const_int 0)])
(define_insn "branch_zero_inverted"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:SI 0 "cmp_op"
[(match_operand:SI 2 "register_operand" "d")
(const_int 0)])
(define_insn "branch_zero_di"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:DI 0 "cmp_op"
[(match_operand:DI 2 "se_register_operand" "d")
(const_int 0)])
(define_insn "branch_zero_di_inverted"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:DI 0 "cmp_op"
[(match_operand:DI 2 "se_register_operand" "d")
(const_int 0)])
(define_insn "branch_equality"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:SI 0 "equality_op"
[(match_operand:SI 2 "register_operand" "d")
(match_operand:SI 3 "register_operand" "d")])
(define_insn "branch_equality_di"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:DI 0 "equality_op"
[(match_operand:DI 2 "se_register_operand" "d")
(match_operand:DI 3 "se_register_operand" "d")])
(define_insn "branch_equality_inverted"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:SI 0 "equality_op"
[(match_operand:SI 2 "register_operand" "d")
(match_operand:SI 3 "register_operand" "d")])
(define_insn "branch_equality_di_inverted"
[(set (pc)
- (if_then_else
+ (if_then_else
(match_operator:DI 0 "equality_op"
[(match_operand:DI 2 "se_register_operand" "d")
(match_operand:DI 3 "se_register_operand" "d")])
in a switch table, then used in a `j' instruction. */
else if (mips_abi != ABI_32 && mips_abi != ABI_O64)
return \"%*b\\t%l0\";
- else
+ else
return \"%*j\\t%l0\";
}"
[(set_attr "type" "jump")
/* Do the PIC jump. */
if (Pmode != DImode)
- emit_jump_insn (gen_casesi_internal (reg, operands[3],
+ emit_jump_insn (gen_casesi_internal (reg, operands[3],
gen_reg_rtx (SImode)));
else
- emit_jump_insn (gen_casesi_internal_di (reg, operands[3],
+ emit_jump_insn (gen_casesi_internal_di (reg, operands[3],
gen_reg_rtx (DImode)));
DONE;
(define_insn "casesi_internal_di"
[(set (pc)
- (mem:DI (plus:DI (sign_extend:DI
+ (mem:DI (plus:DI (sign_extend:DI
(mult:SI (match_operand:SI 0 "register_operand" "d")
(const_int 4)))
(label_ref (match_operand 1 "" "")))))
"TARGET_ABICALLS && Pmode == DImode"
"")
-;; For o32/n32/n64, we need to arrange for longjmp to put the
+;; For o32/n32/n64, we need to arrange for longjmp to put the
;; target address in t9 so that we can use it for loading $gp.
(define_expand "builtin_longjmp"
}"
[(set_attr "type" "jump")
(set_attr "mode" "none")])
-
+
;; When generating embedded PIC code we need to get the address of the
;; current function. This specialized instruction does just that.
(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
(match_operand 2 "" "i")))
(clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_MIPS16
+ "!TARGET_MIPS16
&& !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS"
"%*jal\\t%3,%1"
[(set_attr "type" "call")
(call (mem:DI (match_operand:DI 1 "se_register_operand" "r"))
(match_operand 2 "" "i")))
(clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_MIPS16
+ "!TARGET_MIPS16
&& Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS"
"%*jal\\t%3,%1"
[(set_attr "type" "call")
;; operands[0] = gen_reg_rtx (SImode);
;; operands[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
;; MEM_VOLATILE_P (operands[1]) = TRUE;
-;;
+;;
;; /* fall through and generate default code */
;; }")
;;
(if_then_else:DI (match_dup 5)
(match_operand:DI 2 "se_reg_or_0_operand" "")
(match_operand:DI 3 "se_reg_or_0_operand" "")))]
- "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
+ "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
"
{
gen_conditional_move (operands);
projects / thirdparty / gcc.git / commitdiff
