clk: clk-axi-clkgen: fix coding style issues

This is just cosmetics and so no functional changes intended.

While at it, sort header in alphabetical order.

Signed-off-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20250519-dev-axi-clkgen-limits-v6-7-bc4b3b61d1d4@analog.com
Reviewed-by: David Lechner <dlechner@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c
index 63951209c460f26ed3940879da536e31ae530188..2bb52c4dc7be5167380c1d158d96c7618d16c558 100644 (file)
--- a/drivers/clk/clk-axi-clkgen.c
+++ b/drivers/clk/clk-axi-clkgen.c
@@ -8,15 +8,15 @@
 
 #include <linux/adi-axi-common.h>
 #include <linux/bits.h>
-#include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
-#include <linux/slab.h>
+#include <linux/err.h>
 #include <linux/io.h>
-#include <linux/of.h>
 #include <linux/module.h>
 #include <linux/mod_devicetable.h>
-#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
 
 #define AXI_CLKGEN_V2_REG_RESET                0x40
 #define AXI_CLKGEN_V2_REG_CLKSEL       0x44
@@ -96,7 +96,7 @@ static uint32_t axi_clkgen_lookup_filter(unsigned int m)
        }
 }
 
-static const uint32_t axi_clkgen_lock_table[] = {
+static const u32 axi_clkgen_lock_table[] = {
        0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
        0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
        0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
@@ -108,7 +108,7 @@ static const uint32_t axi_clkgen_lock_table[] = {
        0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
 };
 
-static uint32_t axi_clkgen_lookup_lock(unsigned int m)
+static u32 axi_clkgen_lookup_lock(unsigned int m)
 {
        if (m < ARRAY_SIZE(axi_clkgen_lock_table))
                return axi_clkgen_lock_table[m];
@@ -130,8 +130,9 @@ static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = {
 };
 
 static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits,
-       unsigned long fin, unsigned long fout,
-       unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
+                                  unsigned long fin, unsigned long fout,
+                                  unsigned int *best_d, unsigned int *best_m,
+                                  unsigned int *best_dout)
 {
        unsigned long d, d_min, d_max, _d_min, _d_max;
        unsigned long m, m_min, m_max;
@@ -198,9 +199,9 @@ struct axi_clkgen_div_params {
 };
 
 static void axi_clkgen_calc_clk_params(unsigned int divider,
-       unsigned int frac_divider, struct axi_clkgen_div_params *params)
+                                      unsigned int frac_divider,
+                                      struct axi_clkgen_div_params *params)
 {
-
        memset(params, 0x0, sizeof(*params));
 
        if (divider == 1) {
@@ -228,7 +229,7 @@ static void axi_clkgen_calc_clk_params(unsigned int divider,
                if (params->edge == 0 || frac_divider == 1)
                        params->low--;
                if (((params->edge == 0) ^ (frac_divider == 1)) ||
-                       (divider == 2 && frac_divider == 1))
+                   (divider == 2 && frac_divider == 1))
                        params->frac_wf_f = 1;
 
                params->frac_phase = params->edge * 4 + frac_divider / 2;
@@ -236,13 +237,13 @@ static void axi_clkgen_calc_clk_params(unsigned int divider,
 }
 
 static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
-       unsigned int reg, unsigned int val)
+                            unsigned int reg, unsigned int val)
 {
        writel(val, axi_clkgen->base + reg);
 }
 
 static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
-       unsigned int reg, unsigned int *val)
+                           unsigned int reg, unsigned int *val)
 {
        *val = readl(axi_clkgen->base + reg);
 }
@@ -263,7 +264,7 @@ static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
 }
 
 static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
-       unsigned int reg, unsigned int *val)
+                               unsigned int reg, unsigned int *val)
 {
        unsigned int reg_val;
        int ret;
@@ -287,7 +288,8 @@ static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
 }
 
 static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
-       unsigned int reg, unsigned int val, unsigned int mask)
+                                unsigned int reg, unsigned int val,
+                                unsigned int mask)
 {
        unsigned int reg_val = 0;
        int ret;
@@ -308,8 +310,7 @@ static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
        return 0;
 }
 
-static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
-       bool enable)
+static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen, bool enable)
 {
        unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
 
@@ -325,31 +326,31 @@ static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
 }
 
 static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen,
-       unsigned int reg1, unsigned int reg2, unsigned int reg3,
-       struct axi_clkgen_div_params *params)
+                              unsigned int reg1, unsigned int reg2,
+                              unsigned int reg3,
+                              struct axi_clkgen_div_params *params)
 {
        axi_clkgen_mmcm_write(axi_clkgen, reg1,
-               (params->high << 6) | params->low, 0xefff);
+                             (params->high << 6) | params->low, 0xefff);
        axi_clkgen_mmcm_write(axi_clkgen, reg2,
-               (params->frac << 12) | (params->frac_en << 11) |
-               (params->frac_wf_r << 10) | (params->edge << 7) |
-               (params->nocount << 6), 0x7fff);
+                             (params->frac << 12) | (params->frac_en << 11) |
+                             (params->frac_wf_r << 10) | (params->edge << 7) |
+                             (params->nocount << 6), 0x7fff);
        if (reg3 != 0) {
                axi_clkgen_mmcm_write(axi_clkgen, reg3,
-                       (params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00);
+                                     (params->frac_phase << 11) | (params->frac_wf_f << 10),
+                                     0x3c00);
        }
 }
 
-static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
-       unsigned long rate, unsigned long parent_rate)
+static int axi_clkgen_set_rate(struct clk_hw *clk_hw, unsigned long rate,
+                              unsigned long parent_rate)
 {
        struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
        const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
        unsigned int d, m, dout;
        struct axi_clkgen_div_params params;
-       uint32_t power = 0;
-       uint32_t filter;
-       uint32_t lock;
+       u32 power = 0, filter, lock;
 
        if (parent_rate == 0 || rate == 0)
                return -EINVAL;
@@ -369,22 +370,22 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
 
        axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, &params);
        axi_clkgen_set_div(axi_clkgen,  MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2,
-               MMCM_REG_CLKOUT5_2, &params);
+                          MMCM_REG_CLKOUT5_2, &params);
 
        axi_clkgen_calc_clk_params(d, 0, &params);
        axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
-               (params.edge << 13) | (params.nocount << 12) |
-               (params.high << 6) | params.low, 0x3fff);
+                             (params.edge << 13) | (params.nocount << 12) |
+                             (params.high << 6) | params.low, 0x3fff);
 
        axi_clkgen_calc_clk_params(m >> 3, m & 0x7, &params);
        axi_clkgen_set_div(axi_clkgen,  MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2,
-               MMCM_REG_CLKOUT6_2, &params);
+                          MMCM_REG_CLKOUT6_2, &params);
 
        axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
        axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
-               (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
+                             (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
        axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
-               (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
+                             (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
        axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
        axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);
 
@@ -413,7 +414,7 @@ static int axi_clkgen_determine_rate(struct clk_hw *hw,
 }
 
 static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
-       unsigned int reg1, unsigned int reg2)
+                                      unsigned int reg1, unsigned int reg2)
 {
        unsigned int val1, val2;
        unsigned int div;
@@ -440,7 +441,7 @@ static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
 }
 
 static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
-       unsigned long parent_rate)
+                                           unsigned long parent_rate)
 {
        struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
        unsigned int d, m, dout;
@@ -448,9 +449,9 @@ static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
        unsigned int val;
 
        dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1,
-               MMCM_REG_CLKOUT0_2);
+                                 MMCM_REG_CLKOUT0_2);
        m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1,
-               MMCM_REG_CLK_FB2);
+                              MMCM_REG_CLK_FB2);
 
        axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val);
        if (val & MMCM_CLK_DIV_NOCOUNT)
@@ -623,7 +624,7 @@ static int axi_clkgen_probe(struct platform_device *pdev)
 
        clk_name = pdev->dev.of_node->name;
        of_property_read_string(pdev->dev.of_node, "clock-output-names",
-               &clk_name);
+                               &clk_name);
 
        init.name = clk_name;
        init.ops = &axi_clkgen_ops;