arm: improve tests for vcmulq*

gcc/testsuite/ChangeLog:

	* gcc.target/arm/mve/intrinsics/vcmulq_f16.c: Use
	check-function-bodies instead of scan-assembler checks.  Use
	extern "C" for C++ testing.
	* gcc.target/arm/mve/intrinsics/vcmulq_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c: Likewise.
	* gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c
index 142c315ecf50ab7b693e49600dbca0b70b234955..456370e1de1adadb2fc4de4b33d17f03f4b00caf 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vcmul.f16       q[0-9]+, q[0-9]+, q[0-9]+, #0(?:        @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmulq_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vcmul.f16       q[0-9]+, q[0-9]+, q[0-9]+, #0(?:        @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c
index 158d750793d07a77b90fda0a222548bab567799a..64db652a1a1b8aafa392bc23288dc2b0f771a57e 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vcmul.f32       q[0-9]+, q[0-9]+, q[0-9]+, #0(?:        @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmulq_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vcmul.f32       q[0-9]+, q[0-9]+, q[0-9]+, #0(?:        @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmulq (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c
index b38e0d9fb5260ef8c8aaa4cb8db79b714b9232f1..b60f5d718f85b7baf4479bfc1cc68271381fb9f7 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #0(?:        @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #0(?:        @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c
index 7bf68735e5234d0b9bf74abc71e34978e80ee6c8..22157d4e58fa6f8c0cc3d0818fca60af1f59720c 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #0(?:        @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #0(?:        @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c
index fc7162aaa9c792fc0c14107f47b899594d406d0f..f01b0f3421f46211613e0e343236240cde0d8615 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vcmul.f16       q[0-9]+, q[0-9]+, q[0-9]+, #180(?:      @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot180_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vcmul.f16       q[0-9]+, q[0-9]+, q[0-9]+, #180(?:      @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot180 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c
index 13a4553b6bdfac97d7801fb50288b2eb3370e449..537385c520954b546085ec6e81a59d8f84aefb6e 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vcmul.f32       q[0-9]+, q[0-9]+, q[0-9]+, #180(?:      @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot180_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vcmul.f32       q[0-9]+, q[0-9]+, q[0-9]+, #180(?:      @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot180 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c
index 8767e2beee8f7b0af76648ff7eae2e58f2b54eb1..bc8692eb0430995906107fc99044cac90d401f71 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #180(?:      @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #180(?:      @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c
index 3f951039f357edd234009b40a702abf436ae096b..d2a0b6d3f2ccb20bf3b4ff15b7edecb5386246ba 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #180(?:      @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #180(?:      @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c
index f8e835f158f5bed733b2361e73bf01474ae0f51f..37d7b79a75c5e8306c89881baf00539cff40feb4 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #180(?:      @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #180(?:      @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c
index d0d30c59d446fbe17c5ab52a500a5ab69f304099..1e57fba4bd395644435d21f6d50d65e3b5bbef77 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #180(?:      @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #180(?:      @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot180_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c
index 225b8910f88dbe30cc4f575856e6c31f7d5e7dfc..05c444af804343ebebf547ef0dca6c9353dc3a41 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vcmul.f16       q[0-9]+, q[0-9]+, q[0-9]+, #270(?:      @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot270_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vcmul.f16       q[0-9]+, q[0-9]+, q[0-9]+, #270(?:      @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c
index 1c8b0ebcf7e7a76593b6c5f85db572c5129a95e3..b599c9fc17191856107683a38b594d9b4737d072 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vcmul.f32       q[0-9]+, q[0-9]+, q[0-9]+, #270(?:      @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot270_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vcmul.f32       q[0-9]+, q[0-9]+, q[0-9]+, #270(?:      @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot270 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c
index 20ccb5e94239b8c9f43e7c767a32d2c279975614..fded8a05089acaa4aebcfb00499508c00cab6b1c 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #270(?:      @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #270(?:      @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c
index 7499f4271a6ed86543daa63034af34e02f007ad1..54d939eb378218c9656e09328fc741f15d5df2a7 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #270(?:      @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #270(?:      @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c
index d1b52e74d6d35c94d44f1e422c7a0a6e6793001f..d1e58cb84bba4694ff68a02d77aaa292e5e8a25e 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #270(?:      @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #270(?:      @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c
index 35da5936f66a704b8b8d2a6aae2dff5a10ab053c..07c781f5103efe8a4b06d5dd9b9d379e0a19d9ef 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #270(?:      @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #270(?:      @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot270_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c
index 17f96cb0a7817c23f3a06c2237133f09cf9996e3..53b1930c045180067849d2d1126c88c84aad6432 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f16.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vcmul.f16       q[0-9]+, q[0-9]+, q[0-9]+, #90(?:       @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot90_f16 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vcmul.f16       q[0-9]+, q[0-9]+, q[0-9]+, #90(?:       @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b)
 {
   return vcmulq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c
index 739fc9cd1fa0151d184141d62010982afe4c3f42..147f1807c29bd6620b615ce19725e4c6d13281a5 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_f32.c
@@ -1,21 +1,41 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vcmul.f32       q[0-9]+, q[0-9]+, q[0-9]+, #90(?:       @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot90_f32 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vcmul.f32       q[0-9]+, q[0-9]+, q[0-9]+, #90(?:       @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b)
 {
   return vcmulq_rot90 (a, b);
 }
 
-/* { dg-final { scan-assembler "vcmul.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c
index 8259baa82cc84a2c739c57ac94a0d49f0f4a8031..8c4b0902b09006251d1b5358086bff6bd3fb082c 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #90(?:       @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_m_f16 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #90(?:       @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c
index 751a9a6c03dee567676eb7c670819102acba0425..b3131a5e984bc4a195334ae76ae69532d0af1815 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_m_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #90(?:       @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_m_f32 (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #90(?:       @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_m (inactive, a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c
index c4aef6cbf30ab1313bfaccb58db7fa31276f41d0..000610367b97b4c55c0a0e24f8bae0e2fb98699a 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #90(?:       @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #90(?:       @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c
index 9c54f0870e7b95ac72c3794c584e3c2cf2451baa..8e31ad563c6d276c92c3aec352b6684f622c20ec 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c
@@ -1,23 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #90(?:       @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #90(?:       @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_rot90_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c
index 7634d61b6ea6812caa9df8d825b467f50640300e..b53324738f21c798c9d5cd5efaaed8543e8ab696 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #0(?:        @.*|)
+**     ...
+*/
 float16x8_t
 foo (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_x_f16 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f16"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f16      q[0-9]+, q[0-9]+, q[0-9]+, #0(?:        @.*|)
+**     ...
+*/
 float16x8_t
 foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p)
 {
   return vcmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file

diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c
index 21b6acf9733a4fb2a49dbdf925c052bafdd7841f..a73482a09e1ebf5ca01ac56756b7a4083a0301c7 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c
@@ -1,22 +1,49 @@
 /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
 /* { dg-add-options arm_v8_1m_mve_fp } */
 /* { dg-additional-options "-O2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
 
 #include "arm_mve.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+**foo:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #0(?:        @.*|)
+**     ...
+*/
 float32x4_t
 foo (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_x_f32 (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
-/* { dg-final { scan-assembler "vcmult.f32"  }  } */
 
+/*
+**foo1:
+**     ...
+**     vmsr    p0, (?:ip|fp|r[0-9]+)(?:        @.*|)
+**     ...
+**     vpst(?: @.*|)
+**     ...
+**     vcmult.f32      q[0-9]+, q[0-9]+, q[0-9]+, #0(?:        @.*|)
+**     ...
+*/
 float32x4_t
 foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p)
 {
   return vcmulq_x (a, b, p);
 }
 
-/* { dg-final { scan-assembler "vpst" } } */
+#ifdef __cplusplus
+}
+#endif
+
+/* { dg-final { scan-assembler-not "__ARM_undef" } } */
\ No newline at end of file