[AArch64] Initial commit for Morello architecture

The Morello architecture implements support for 129 bit capabilities
to replace traditional pointers to reference memory.  A 129 bit
capability has a 64-bit virtual address in its lowest bits and the
next 64 bits have various access control metadata such as bounds
within which the virtual address can be, permissions and other
metadata for protection.  The top 129th bit is stored out of band and
it indicates if the capability is valid.

Capability registers extends the 64-bit register file and are
similarly numberd c0 to c30.  The stack capability register is csp and
it aliases with sp.  One may access the lower 64 bits of the
capability registers by using the 64-bit register names, i.e. x0-x30
and sp.  The Arm Architecture Reference Manual Supplement Morello for
A-profile Architecture has more details on the register layout.

To ensure backward compatibiility, processors implementing the Morello
architecture can run in two states, the standard A64 and a new state
called C64.  In A64 state, base addresses of memory access
instructions are treated as pointers and traditional aarch64
applications should run out of the box in this state.  In C64 state,
base address registers are expected to be valid capabilities.

There are additional load and store instructions that allow using
capabilities as address registers in A64 mode (and 64-bit registers in
C64 mode).  These are called alternate base loads and stores.

The following new -march flags are implemented:

- a64c: This is the base feature flag to implement instruction
  extensions for Morello that are distinct from its base A64 support.
  Address registers are assumed to be 64-bit except for alternate base
  loads and stores; they are assumed to be capability registers.

- morello: This enables instructions that are allowed on the Morello
  architecture in A64.  This includes armv8.2-a, a64c and other
  extensions that are considered part of the Morello architecture.

- c64: This enables instructions that are allowed on the Morello
  architecture in C64 state.  Address registers are assumed to be
  capabilities except for alternate base loads and stores; they are
  assumed to be 64-bit registers.

To assemble code that is intended to run in A64 state on Morello,
build with -march=morello and for C64 state, build with
-march=morello+c64.

This patch implements bare support for registers and the -march flags.

gas/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* config/tc-aarch64.c (AARCH64_REG_TYPES,
	get_reg_expected_msg, aarch64_addr_reg_parse, parse_address,
	reg_names): Add capability registers.
	(parse_operands): Identify capability register based address.
	(aarch64_archs): Add morello.
	(aarch64_features): Add a64c and c64.
	* doc/c-aarch64.texi: Document -march flags.
	* testsuite/gas/aarch64/morello_insn.d: New file
	* testsuite/gas/aarch64/morello_insn-c64.d: New file
	* testsuite/gas/aarch64/morello_insn.s: New file.

include/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_A64C,
	AARCH64_FEATURE_C64): New feature macros.
	(AARCH64_ARCH_MORELLO): New architecture macro.
	(aarch64_operand_class): Add AARCH64_OPND_CLASS_CAP_REG.
	(aarch64_opnd): New capability operands.
	(aarch64_opnd_qualifier): New capability qualifier.
	(aarch64_insn_class): Add a64c instruction class.

opcodes/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* aarch64-opc.c (fields): New capability register fields.
	(aarch64_opnd_qualifiers): Capability operand qualifiers.
	(int_reg): Add capability register bank.
	(get_int_reg_name): Adjust for capability registers.
	(get_cap_reg_name): New function.
	(aarch64_print_operand): Support printing capability operands.
	* aarch64-opc.h (aarch64_field_kind): Add capability operand
	fields.
	(OPD_F_MAYBE_CSP): New macro.
	(operand_maybe_cap_stack_pointer): New function.
	* aarch64-tbl.h (QL2_A64C_CA_CA, A64C, A64C_INSN): New macros.
	(aarch64_feature_a64c): New feature set.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3792e04a90f75bca27ac590bbe33a6f2bdc6b136..98d2586cffaa91d0a0de880af3f7dc050b16b9a5 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,16 @@
+2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
+
+       * config/tc-aarch64.c (AARCH64_REG_TYPES,
+       get_reg_expected_msg, aarch64_addr_reg_parse, parse_address,
+       reg_names): Add capability registers.
+       (parse_operands): Identify capability register based address.
+       (aarch64_archs): Add morello.
+       (aarch64_features): Add a64c and c64.
+       * doc/c-aarch64.texi: Document -march flags.
+       * testsuite/gas/aarch64/morello_insn.d: New file
+       * testsuite/gas/aarch64/morello_insn-c64.d: New file
+       * testsuite/gas/aarch64/morello_insn.s: New file.
+
 2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
 
        * config/tc-aarch64.c (output_operand_error_report): Account

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 8ef295a9b99ba35d892c24d1ac8c7b838a17bcb5..9811a50027624d2ef63d0559d5ad0cc502d5aa9a 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -279,6 +279,10 @@ struct reloc_entry
   BASIC_REG_TYPE(FP_S) /* s[0-31] */   \
   BASIC_REG_TYPE(FP_D) /* d[0-31] */   \
   BASIC_REG_TYPE(FP_Q) /* q[0-31] */   \
+  BASIC_REG_TYPE(CA_N) /* c[0-30] */   \
+  BASIC_REG_TYPE(CA_SP)        /* csp     */   \
+  BASIC_REG_TYPE(CA_Z) /* czr     */   \
+  BASIC_REG_TYPE(CA_D) /* ddc     */   \
   BASIC_REG_TYPE(VN)   /* v[0-31] */   \
   BASIC_REG_TYPE(ZN)   /* z[0-31] */   \
   BASIC_REG_TYPE(PN)   /* p[0-15] */   \
@@ -325,6 +329,9 @@ struct reloc_entry
   MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64)                  \
                 | REG_TYPE(SP_32) | REG_TYPE(SP_64)                    \
                 | REG_TYPE(Z_32) | REG_TYPE(Z_64))                     \
+  /* Typecheck: any capability register (inc CSP) */                   \
+  MULTI_REG_TYPE(CA_N_SP, REG_TYPE(CA_N) | REG_TYPE(CA_SP))            \
+  MULTI_REG_TYPE(CA_N_Z, REG_TYPE(CA_N) | REG_TYPE(CA_Z))              \
   /* Pseudo type to mark the end of the enumerator sequence.  */       \
   BASIC_REG_TYPE(MAX)
 
@@ -439,6 +446,18 @@ get_reg_expected_msg (aarch64_reg_type reg_type)
     case REG_TYPE_PN:
       msg = N_("SVE predicate register expected");
       break;
+    case REG_TYPE_CA_N:
+      msg = N_("Capability register C0 - C30 expected");
+      break;
+    case REG_TYPE_CA_SP:
+      msg = N_("Capability register CSP expected");
+      break;
+    case REG_TYPE_CA_N_SP:
+      msg = N_("Capability register C0 - C30 or CSP expected");
+      break;
+    case REG_TYPE_CA_Z:
+      msg = N_("Capability register CZR expected");
+      break;
     default:
       as_fatal (_("invalid register type %d"), reg_type);
     }
@@ -797,6 +816,11 @@ aarch64_addr_reg_parse (char **ccp, aarch64_reg_type reg_type,
       str += 2;
       break;
 
+    case REG_TYPE_CA_N:
+    case REG_TYPE_CA_SP:
+      *qualifier = AARCH64_OPND_QLF_CA;
+      break;
+
     default:
       return NULL;
     }
@@ -3901,8 +3925,16 @@ static bool
 parse_address (char **str, aarch64_opnd_info *operand)
 {
   aarch64_opnd_qualifier_t base_qualifier, offset_qualifier;
+
+  aarch64_reg_type base;
+
+  if (AARCH64_CPU_HAS_FEATURE (cpu_variant, AARCH64_FEATURE_C64))
+    base = REG_TYPE_CA_N_SP;
+  else
+    base = REG_TYPE_R64_SP;
+
   return parse_address_main (str, operand, &base_qualifier, &offset_qualifier,
-                            REG_TYPE_R64_SP, REG_TYPE_R_Z, SHIFTED_NONE);
+                            base, REG_TYPE_R_Z, SHIFTED_NONE);
 }
 
 /* Parse an address in which SVE vector registers and MUL VL are allowed.
@@ -7005,7 +7037,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
            /* Then retry, matching the specific syntax of these addresses.  */
            str = start;
            po_char_or_fail ('[');
-           po_reg_or_fail (REG_TYPE_R64_SP);
+           po_reg_or_fail (AARCH64_CPU_HAS_FEATURE (cpu_variant,
+                                                    AARCH64_FEATURE_C64)
+                           ? REG_TYPE_CA_N_SP : REG_TYPE_R64_SP);
+
            /* Accept optional ", #0".  */
            if (operands[i] == AARCH64_OPND_ADDR_SIMPLE
                && skip_past_char (&str, ','))
@@ -8164,6 +8199,13 @@ static const reg_entry reg_names[] = {
   REGDEF (wzr, 31, Z_32), REGDEF (WZR, 31, Z_32),
   REGDEF (xzr, 31, Z_64), REGDEF (XZR, 31, Z_64),
 
+  /* Capability Registers.  */
+  REGSET31 (c, CA_N), REGSET31 (C, CA_N),
+  REGDEF (csp, 31, CA_SP), REGDEF (CSP, 31, CA_SP),
+  REGDEF (czr, 31, CA_Z), REGDEF (CZR, 31, CA_Z),
+  REGDEF (ddc, 33, CA_D), REGDEF (DDC, 33, CA_D),
+  REGDEF_ALIAS (clr, 30, CA_N), REGDEF_ALIAS (CLR, 30, CA_N),
+
   /* Floating-point single precision registers.  */
   REGSET (s, FP_S), REGSET (S, FP_S),
 
@@ -9899,6 +9941,7 @@ static const struct aarch64_arch_option_table aarch64_archs[] = {
   {"armv9.1-a",        AARCH64_ARCH_V9_1},
   {"armv9.2-a",        AARCH64_ARCH_V9_2},
   {"armv9.3-a",        AARCH64_ARCH_V9_3},
+  {"morello", AARCH64_ARCH_MORELLO},
   {NULL, AARCH64_ARCH_NONE}
 };
 
@@ -10009,6 +10052,10 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
                        AARCH64_ARCH_NONE},
   {"hbc",              AARCH64_FEATURE (AARCH64_FEATURE_HBC, 0),
                        AARCH64_ARCH_NONE},
+  {"a64c",             AARCH64_FEATURE (AARCH64_FEATURE_A64C, 0),
+                       AARCH64_ARCH_NONE},
+  {"c64",              AARCH64_FEATURE (AARCH64_FEATURE_C64, 0),
+                       AARCH64_FEATURE (AARCH64_FEATURE_A64C, 0)},
   {NULL,               AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
 };
 

diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 0809310a9a3b3c1776bc62417865e691080bd251..7f4599d453007b498093663283e9aa92940cb57b 100644 (file)
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -112,7 +112,7 @@ following architecture names are recognized: @code{armv8-a},
 @code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
 @code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8.8-a},
 @code{armv8-r}, @code{armv9-a}, @code{armv9.1-a}, @code{armv9.2-a},
-and @code{armv9.3-a}.
+@code{armv9.3-a}, @code{a64c}, @code{c64}, and @code{morello}.
 
 If both @option{-mcpu} and @option{-march} are specified, the
 assembler will use the setting for @option{-mcpu}.  If neither are

diff --git a/gas/testsuite/gas/aarch64/morello_insn-c64.d b/gas/testsuite/gas/aarch64/morello_insn-c64.d
new file mode 100644 (file)
index 0000000..a642cbb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/morello_insn-c64.d
@@ -0,0 +1,11 @@
+#as: -march=morello+c64
+#objdump: -dr
+#source: morello_insn.s
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+.* <.text>:
+.*:    d503201f        nop

diff --git a/gas/testsuite/gas/aarch64/morello_insn.d b/gas/testsuite/gas/aarch64/morello_insn.d
new file mode 100644 (file)
index 0000000..b695248
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/morello_insn.d
@@ -0,0 +1,10 @@
+#as: -march=morello
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+.* <.text>:
+.*:    d503201f        nop

diff --git a/gas/testsuite/gas/aarch64/morello_insn.s b/gas/testsuite/gas/aarch64/morello_insn.s
new file mode 100644 (file)
index 0000000..c27745a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/morello_insn.s
@@ -0,0 +1 @@
+nop

diff --git a/include/ChangeLog b/include/ChangeLog
index 502fc47c148ee776fe0b76bac772d0d66da69d99..472741f9b92e2b68226c6e022790e6cd611d49e0 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,13 @@
+2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
+
+       * opcode/aarch64.h (AARCH64_FEATURE_A64C,
+       AARCH64_FEATURE_C64): New feature macros.
+       (AARCH64_ARCH_MORELLO): New architecture macro.
+       (aarch64_operand_class): Add AARCH64_OPND_CLASS_CAP_REG.
+       (aarch64_opnd): New capability operands.
+       (aarch64_opnd_qualifier): New capability qualifier.
+       (aarch64_insn_class): Add a64c instruction class.
+
 2022-04-01  John Baldwin  <jhb@FreeBSD.org>
 
        * elf/common.h (NT_FREEBSD_X86_SEGBASES): Define.

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index a4912930c8f1e564bec6ec46a649ac1205093bd1..53681a7abc5b90fb10fe662ebc3023c1ba744256 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -98,6 +98,10 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_SME_I64             (1ULL << 58) /* SME I64.  */
 #define AARCH64_FEATURE_V8_8        (1ULL << 59) /* Armv8.8 processors.  */
 
+/* Capability extensions.  */
+#define AARCH64_FEATURE_A64C         (1ULL << 60)
+#define AARCH64_FEATURE_C64          (1ULL << 61)
+
 /* Crypto instructions are the combination of AES and SHA2.  */
 #define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
 
@@ -178,6 +182,13 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_ARCH_V9_3      AARCH64_FEATURE (AARCH64_ARCH_V9_2,     \
                                                 AARCH64_ARCH_V9_3_FEATURES)
 
+#define AARCH64_ARCH_MORELLO   AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
+                                                AARCH64_FEATURE_A64C   \
+                                                | AARCH64_FEATURE_F16_FML \
+                                                | AARCH64_FEATURE_DOTPROD \
+                                                | AARCH64_FEATURE_RCPC \
+                                                | AARCH64_FEATURE_SSBS)
+
 #define AARCH64_ARCH_NONE      AARCH64_FEATURE (0, 0)
 #define AARCH64_ANY            AARCH64_FEATURE (-1, 0) /* Any basic core.  */
 
@@ -225,6 +236,7 @@ enum aarch64_operand_class
   AARCH64_OPND_CLASS_IMMEDIATE,
   AARCH64_OPND_CLASS_SYSTEM,
   AARCH64_OPND_CLASS_COND,
+  AARCH64_OPND_CLASS_CAP_REG,
 };
 
 /* Operand code that helps both parsing and coding.
@@ -489,7 +501,19 @@ enum aarch64_opnd
   AARCH64_OPND_SM3_IMM2,       /* SM3 encodes lane in bits [13, 14].  */
   AARCH64_OPND_MOPS_ADDR_Rd,   /* [Rd]!, in bits [0, 4].  */
   AARCH64_OPND_MOPS_ADDR_Rs,   /* [Rs]!, in bits [16, 20].  */
-  AARCH64_OPND_MOPS_WB_Rn      /* Rn!, in bits [5, 9].  */
+  AARCH64_OPND_MOPS_WB_Rn,     /* Rn!, in bits [5, 9].  */
+
+  AARCH64_OPND_Cad,             /* A capability register as destination.  */
+  AARCH64_OPND_Cam,             /* Capability register as source.  */
+  AARCH64_OPND_Can,             /* Capability register as source.  */
+  AARCH64_OPND_Cas,             /* A capability register.  */
+  AARCH64_OPND_Cat,             /* Capability register destination in load
+                                  store instructions.  */
+  AARCH64_OPND_Cat2,            /* Capability register destination 2 in load
+                                  store instructions.  */
+  AARCH64_OPND_Cad_SP,          /* Capability register or Cap SP as
+                                  destination.  */
+  AARCH64_OPND_Can_SP,         /* Capability register or Cap SP as source. */
 };
 
 /* Qualifier constrains an operand.  It either specifies a variant of an
@@ -558,6 +582,9 @@ enum aarch64_opnd_qualifier
      like in stg, st2g, etc.   */
   AARCH64_OPND_QLF_imm_tag,
 
+  /* Capability Registers.  */
+  AARCH64_OPND_QLF_CA,
+
   /* Constraint on value.  */
   AARCH64_OPND_QLF_CR,         /* CRn, CRm. */
   AARCH64_OPND_QLF_imm_0_7,
@@ -681,6 +708,7 @@ enum aarch64_insn_class
   cryptosm4,
   dotproduct,
   bfloat16,
+  a64c,
 };
 
 /* Opcode enumerators.  */

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a16a93749d77c1889d91035b5e3b428dddb82af1..b4121c46c061ebd1e063707c55b1d4a4eb52f903 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,18 @@
+2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>
+
+       * aarch64-opc.c (fields): New capability register fields.
+       (aarch64_opnd_qualifiers): Capability operand qualifiers.
+       (int_reg): Add capability register bank.
+       (get_int_reg_name): Adjust for capability registers.
+       (get_cap_reg_name): New function.
+       (aarch64_print_operand): Support printing capability operands.
+       * aarch64-opc.h (aarch64_field_kind): Add capability operand
+       fields.
+       (OPD_F_MAYBE_CSP): New macro.
+       (operand_maybe_cap_stack_pointer): New function.
+       * aarch64-tbl.h (QL2_A64C_CA_CA, A64C, A64C_INSN): New macros.
+       (aarch64_feature_a64c): New feature set.
+
 2022-03-16  Simon Marchi  <simon.marchi@efficios.com>
 
        * configure.ac: Handle bfd_amdgcn_arch.

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 4774eba2e54ce06cd992dd4e165f6d66ab7f3c26..7a8c0c03099844f76c4a4a2341a5333ef265c197 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -342,6 +342,16 @@ const aarch64_field fields[] =
     { 12,  2 }, /* SM3: Indexed element SM3 2 bits index immediate.  */
     { 22,  1 }, /* sz: 1-bit element size select.  */
     { 10,  2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>.  */
+    {  0,  5 }, /* Cad: Capability Destination register.  */
+    {  5,  5 }, /* Can, Capability source register.  */
+    { 16,  5 }, /* Cam, Capability register in load / store and other cap
+                  instructions. */
+    { 16,  5 }, /* Cas, Capability register in some memory / load store
+                  instructions.  */
+    {  0,  5 }, /* Cat, Capability register in load store pair type
+                  instructions.  */
+    { 10,  5 },  /* Cat2, Capability register in destination for load store pair
+                  type instructions.  */
 };
 
 enum aarch64_operand_class
@@ -752,6 +762,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] =
 
   /* Qualifier for scaled immediate for Tag granule (stg,st2g,etc).  */
   {16, 0, 0, "tag", OQK_OPD_VARIANT},
+  {16, 1, 0, "c", OQK_OPD_VARIANT},
 
   /* Qualifiers constraining the value range.
      First 3 fields:
@@ -2899,13 +2910,17 @@ aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd oper
     R (24), R (25), R (26), R (27), R (28), R (29), R (30),  FOR31 }
 /* [0][0]  32-bit integer regs with sp   Wn
    [0][1]  64-bit integer regs with sp   Xn  sf=1
+   [0][2]  129-bit cap regs with sp      Cn
    [1][0]  32-bit integer regs with #0   Wn
-   [1][1]  64-bit integer regs with #0   Xn  sf=1 */
-static const char *int_reg[2][2][32] = {
+   [1][1]  64-bit integer regs with #0   Xn  sf=1
+   [1][2]  129-bit cap regs with #0      Cn  */
+static const char *int_reg[2][3][32] = {
 #define R32(X) "w" #X
 #define R64(X) "x" #X
-  { BANK (R32, "wsp"), BANK (R64, "sp") },
-  { BANK (R32, "wzr"), BANK (R64, "xzr") }
+#define CAP(X) "c" #X
+  { BANK (R32, "wsp"), BANK (R64, "sp"), BANK (CAP, "csp") },
+  { BANK (R32, "wzr"), BANK (R64, "xzr"), BANK (CAP, "czr") }
+#undef CAP
 #undef R64
 #undef R32
 };
@@ -2929,11 +2944,11 @@ static inline const char *
 get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
 {
   const int has_zr = sp_reg_p ? 0 : 1;
-  const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
-  return int_reg[has_zr][is_64][regno];
+  const int bank = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
+  return int_reg[has_zr][bank][regno];
 }
 
-/* Like get_int_reg_name, but IS_64 is always 1.  */
+/* Like get_int_reg_name, but BANK is always 1.  */
 
 static inline const char *
 get_64bit_int_reg_name (int regno, int sp_reg_p)
@@ -2942,6 +2957,14 @@ get_64bit_int_reg_name (int regno, int sp_reg_p)
   return int_reg[has_zr][1][regno];
 }
 
+/* Like get_int_reg_name, but BANK is always 2.  */
+static inline const char *
+get_cap_reg_name (int regno, int sp_reg_p)
+{
+  const int has_zr = sp_reg_p ? 0 : 1;
+  return int_reg[has_zr][2][regno];
+}
+
 /* Get the name of the integer offset register in OPND, using the shift type
    to decide whether it's a word or doubleword.  */
 
@@ -3932,6 +3955,20 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
                get_int_reg_name (opnd->reg.regno, AARCH64_OPND_QLF_X, 0));
       break;
 
+    case AARCH64_OPND_Cad_SP:
+    case AARCH64_OPND_Can_SP:
+      snprintf (buf, size, "%s", get_cap_reg_name (opnd->reg.regno, 1));
+      break;
+
+    case AARCH64_OPND_Cat:
+    case AARCH64_OPND_Cat2:
+    case AARCH64_OPND_Can:
+    case AARCH64_OPND_Cam:
+    case AARCH64_OPND_Cad:
+    case AARCH64_OPND_Cas:
+      snprintf (buf, size, "%s", get_cap_reg_name (opnd->reg.regno, 0));
+      break;
+
     default:
       snprintf (buf, size, "<invalid>");
       break;

diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 126565dca14080b3f1370de7dd42cbc1de90c926..6e4f5187c46eadf0f9026675958cdd4bfa9008a0 100644 (file)
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -168,7 +168,13 @@ enum aarch64_field_kind
   FLD_rotate3,
   FLD_SM3_imm2,
   FLD_sz,
-  FLD_CRm_dsb_nxs
+  FLD_CRm_dsb_nxs,
+  FLD_Cad,
+  FLD_Can,
+  FLD_Cam,
+  FLD_Cas,
+  FLD_Cat,
+  FLD_Cat2,
 };
 
 /* Field description.  */
@@ -219,6 +225,7 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
                                                   value by 2 to get the value
                                                   of an immediate operand.  */
 #define OPD_F_MAYBE_SP         0x00000010      /* May potentially be SP.  */
+#define OPD_F_MAYBE_CSP                0x00000020      /* May potentially be CSP.  */
 #define OPD_F_OD_MASK          0x000000e0      /* Operand-dependent data.  */
 #define OPD_F_OD_LSB           5
 #define OPD_F_NO_ZR            0x00000100      /* ZR index not allowed.  */
@@ -315,6 +322,12 @@ operand_need_shift_by_four (const aarch64_operand *operand)
   return (operand->flags & OPD_F_SHIFT_BY_4) != 0;
 }
 
+static inline bool
+operand_maybe_cap_stack_pointer (const aarch64_operand *operand)
+{
+  return (operand->flags & OPD_F_MAYBE_CSP) != 0;
+}
+
 static inline bool
 operand_maybe_stack_pointer (const aarch64_operand *operand)
 {

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index cb039d63eba3e7a9f04520e29ef77da26ec48f52..7fc59b324c9ebfbc5555f7ccf17eda071aceecee 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2384,6 +2384,11 @@
 {                    \
   QLF3(V_4S, V_8H, S_H),       \
 }
+
+#define QL2_A64C_CA_CA         \
+{                              \
+  QLF2(CA, CA),                        \
+}
 \f
 /* Opcode table.  */
 
@@ -2500,6 +2505,9 @@ static const aarch64_feature_set aarch64_feature_mops_memtag =
 static const aarch64_feature_set aarch64_feature_hbc =
   AARCH64_FEATURE (AARCH64_FEATURE_HBC, 0);
 
+static const aarch64_feature_set aarch64_feature_a64c =
+  AARCH64_FEATURE (AARCH64_FEATURE_A64C, 0);
+
 #define CORE           &aarch64_feature_v8
 #define FP             &aarch64_feature_fp
 #define SIMD           &aarch64_feature_simd
@@ -2553,6 +2561,7 @@ static const aarch64_feature_set aarch64_feature_hbc =
 #define MOPS     &aarch64_feature_mops
 #define MOPS_MEMTAG &aarch64_feature_mops_memtag
 #define HBC      &aarch64_feature_hbc
+#define A64C           &aarch64_feature_a64c
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2686,6 +2695,8 @@ static const aarch64_feature_set aarch64_feature_hbc =
     CONSTRAINTS, 0, VERIFIER }
 #define HBC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, HBC, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define A64C_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, OP, A64C, OPS, QUALS, FLAGS, 0, 0, NULL }
 
 #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
   MOPS_INSN (NAME, OPCODE, MASK, 0, \