RISC-V: Add (u)int8_t to binop tests.

This patch adds the missing (u)int8_t types to the binop tests.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/shift-run.c: Adapt for
	(u)int8_t.
	* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/shift-template.h: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vadd-template.h: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vand-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vand-template.h: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmax-template.h: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmin-template.h: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vmul-template.h: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vor-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vor-template.h: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vrem-template.h: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Dito.
	* gcc.target/riscv/rvv/autovec/binop/vxor-template.h: Dito.

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
index ff3633b530a30c9882e3aedbf03114534f382d05..d7052b2270c5e24b566ad05a625d0ffe182fb2f5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-run.c
@@ -32,12 +32,16 @@
     assert (as##TYPE[i] == (VAL >> (i % 4)));
 
 #define RUN_ALL()      \
+ RUN(int8_t, 1)        \
+ RUN(uint8_t, 2)       \
  RUN(int16_t, 1)       \
  RUN(uint16_t, 2)      \
  RUN(int32_t, 3)       \
  RUN(uint32_t, 4)      \
  RUN(int64_t, 5)       \
  RUN(uint64_t, 6)       \
+ RUN2(int8_t, -7)      \
+ RUN2(uint8_t, 8)      \
  RUN2(int16_t, -7)     \
  RUN2(uint16_t, 8)     \
  RUN2(int32_t, -9)     \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
index 557a7c82531a55abfc813a332961cf3f1420f4a9..befa4b85e8fb58a9e3d8362e760e78a1dd905aa5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c
@@ -3,10 +3,6 @@
 
 #include "shift-template.h"
 
-/* TODO: For int16_t and uint16_t we need widening/promotion patterns.
-   We don't check the assembler number since lacking patterns make
-   auto-vectorization inconsistent in LMUL = 1/2/4/8.  */
-
-/* { dg-final { scan-assembler {\tvsll\.vv} } } */
-/* { dg-final { scan-assembler {\tvsrl\.vv} } } */
-/* { dg-final { scan-assembler {\tvsra\.vv} } } */
+/* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
index 01a9cb21efc086ab2b00815eae99793f6f53823f..976b29fa356508021b803ef0dc0618d9bbff0714 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c
@@ -3,6 +3,6 @@
 
 #include "shift-template.h"
 
-/* { dg-final { scan-assembler-times {\tvsll\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvsrl\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvsra\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */
+/* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h
index 16ae48c8edecc756c37b2d73590dec864cd0b94c..ca1b96f9f25057b46cea96740cdc804f1bec48aa 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-template.h
@@ -16,14 +16,17 @@
       dst[i] = a[i] >> b[i];                                   \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST1_TYPE(int8_t)    \
+ TEST1_TYPE(uint8_t)   \
  TEST1_TYPE(int16_t)   \
  TEST1_TYPE(uint16_t)  \
  TEST1_TYPE(int32_t)   \
  TEST1_TYPE(uint32_t)  \
  TEST1_TYPE(int64_t)   \
  TEST1_TYPE(uint64_t)   \
+ TEST2_TYPE(int8_t)    \
+ TEST2_TYPE(uint8_t)   \
  TEST2_TYPE(int16_t)   \
  TEST2_TYPE(uint16_t)  \
  TEST2_TYPE(int32_t)   \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
index 8bdc7a220c3d0b5a6226d9862f0174102cd399e5..4f6c8e773c33a8dbc1285e1ff0950dd2b1eeb6da 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-run.c
@@ -44,18 +44,24 @@
     assert (aim##TYPE[i] == VAL - 16);
 
 #define RUN_ALL()      \
+ RUN(int8_t, -1)       \
+ RUN(uint8_t, 2)       \
  RUN(int16_t, -1)      \
  RUN(uint16_t, 2)      \
  RUN(int32_t, -3)      \
  RUN(uint32_t, 4)      \
  RUN(int64_t, -5)      \
  RUN(uint64_t, 6)    \
+ RUN2(int8_t, -7)      \
+ RUN2(uint8_t, 8)      \
  RUN2(int16_t, -7)     \
  RUN2(uint16_t, 8)     \
  RUN2(int32_t, -9)     \
  RUN2(uint32_t, 10)    \
  RUN2(int64_t, -11)    \
  RUN2(uint64_t, 12)   \
+ RUN3M(int8_t, 13)     \
+ RUN3(uint8_t, 14)     \
  RUN3M(int16_t, 13)    \
  RUN3(uint16_t, 14)    \
  RUN3M(int32_t, 15)    \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
index 799ed27ec6df27f4756ed4f844324c2e187a090f..2d094749c6a54c04a3403761ac9f194987e8dbb6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c
@@ -3,5 +3,5 @@
 
 #include "vadd-template.h"
 
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
index 64c2eeec7cf9f2f98bdfed22b8b76284696f0950..4a1dc41c34ad5a859b10a9979ce52f4655049a92 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c
@@ -3,5 +3,5 @@
 
 #include "vadd-template.h"
 
-/* { dg-final { scan-assembler-times {\tvadd\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvadd\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h
index cd945d471d240cc6d23297ba504a3f709014e594..fecf2947691f1e0a3be3de5b7a815ff07c4c57e8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-template.h
@@ -32,20 +32,25 @@
       dst[i] = a[i] - 16;                              \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
  TEST_TYPE(uint32_t)   \
  TEST_TYPE(int64_t)    \
  TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int8_t)    \
+ TEST2_TYPE(uint8_t)   \
  TEST2_TYPE(int16_t)   \
  TEST2_TYPE(uint16_t)  \
  TEST2_TYPE(int32_t)   \
  TEST2_TYPE(uint32_t)  \
  TEST2_TYPE(int64_t)   \
  TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int8_t)   \
+ TEST3_TYPE(uint8_t)   \
  TEST3M_TYPE(int16_t)  \
  TEST3_TYPE(uint16_t)  \
  TEST3M_TYPE(int32_t)  \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
index c13755ed06a11d6b672c0db2b745470266e19d8b..3fa6cf35e181b9bfe65c5739402175e46bfa3a29 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-run.c
@@ -44,18 +44,24 @@
     assert (aim##TYPE[i] == (VAL & -16));
 
 #define RUN_ALL()      \
+ RUN(int8_t, -1)       \
+ RUN(uint8_t, 2)       \
  RUN(int16_t, -1)      \
  RUN(uint16_t, 2)      \
  RUN(int32_t, -3)      \
  RUN(uint32_t, 4)      \
  RUN(int64_t, -5)      \
  RUN(uint64_t, 6)      \
+ RUN2(int8_t, -7)      \
+ RUN2(uint8_t, 8)      \
  RUN2(int16_t, -7)     \
  RUN2(uint16_t, 8)     \
  RUN2(int32_t, -9)     \
  RUN2(uint32_t, 10)    \
  RUN2(int64_t, -11)    \
  RUN2(uint64_t, 12)    \
+ RUN3M(int8_t, 13)     \
+ RUN3(uint8_t, 14)     \
  RUN3M(int16_t, 13)    \
  RUN3(uint16_t, 14)    \
  RUN3M(int32_t, 15)    \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
index 24fc70b4ea4d61456f95a2458023adec9e57cf01..f7636abdec04738ad85dbc385e368db2a9e61e2e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c
@@ -3,5 +3,5 @@
 
 #include "vand-template.h"
 
-/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vi} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
index 67f37c1e170db8d2ad3be409aa7ba3d22a3e96d6..dee8a2d61245e24e2e8879c4dd88a17c81bbcfeb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c
@@ -3,5 +3,5 @@
 
 #include "vand-template.h"
 
-/* { dg-final { scan-assembler-times {\tvand\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvand\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvand\.vi} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h
index 5cabe0730978d5a5a3302bd785c8f1aeda068bb1..e2409594f39fb2039a1996032d810a45c79bb4b8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vand-template.h
@@ -32,20 +32,25 @@
       dst[i] = a[i] & -16;                             \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
  TEST_TYPE(uint32_t)   \
  TEST_TYPE(int64_t)    \
  TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int8_t)    \
+ TEST2_TYPE(uint8_t)   \
  TEST2_TYPE(int16_t)   \
  TEST2_TYPE(uint16_t)  \
  TEST2_TYPE(int32_t)   \
  TEST2_TYPE(uint32_t)  \
  TEST2_TYPE(int64_t)   \
  TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int8_t)   \
+ TEST3_TYPE(uint8_t)   \
  TEST3M_TYPE(int16_t)  \
  TEST3_TYPE(uint16_t)  \
  TEST3M_TYPE(int32_t)  \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
index 5de339172fc2197282d32cf365615637c776524b..c4fd81f4bf2ffb0af85b38e1417b756989fec3d8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-run.c
@@ -28,12 +28,16 @@
     assert (as##TYPE[i] == 5);
 
 #define RUN_ALL()      \
+ RUN(int8_t, -1)       \
+ RUN(uint8_t, 2)       \
  RUN(int16_t, -1)      \
  RUN(uint16_t, 2)      \
  RUN(int32_t, -3)      \
  RUN(uint32_t, 4)      \
  RUN(int64_t, -5)      \
  RUN(uint64_t, 6)      \
+ RUN2(int8_t, -7)      \
+ RUN2(uint8_t, 8)      \
  RUN2(int16_t, -7)     \
  RUN2(uint16_t, 8)     \
  RUN2(int32_t, -9)     \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
index 1dce9dd562ef01cb1a0e2b06fc8f4e6857a225b6..9f059ebc84c43bf3624f6a0bd88f66c544346afd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c
@@ -4,7 +4,7 @@
 #include "vdiv-template.h"
 
 /* Currently we use an epilogue loop which also contains vdivs.  Therefore we
-   expect 10 vdiv[u]s instead of 6.  */
+   expect 14 vdiv[u]s instead of 8.  */
 
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 14 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
index 16a18c466e05e4d01adc4b9a817a159c02324b52..cd5d30b897486807e6cf222c0b4b0b50d2bbbd3b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c
@@ -4,7 +4,7 @@
 #include "vdiv-template.h"
 
 /* Currently we use an epilogue loop which also contains vdivs.  Therefore we
-   expect 10 vdiv[u]s instead of 6.  */
+   expect 14 vdiv[u]s instead of 8.  */
 
-/* { dg-final { scan-assembler-times {\tvdiv\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvdivu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvdiv\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvdivu\.vv} 14 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h
index f8d3bfde4ed67bf0287f697f283cfaa342c16646..fd9199722b6f200c87583fbbb280a527ee3b9345 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-template.h
@@ -17,12 +17,16 @@
   }
 
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
  TEST_TYPE(uint32_t)   \
  TEST_TYPE(int64_t)    \
  TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int8_t)    \
+ TEST2_TYPE(uint8_t)   \
  TEST2_TYPE(int16_t)   \
  TEST2_TYPE(uint16_t)  \
  TEST2_TYPE(int32_t)   \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
index cf184e24b1e16fc27a4ef8276a7eb379e0d0710a..668f848694b57d085469ae371dac5062c51d40fd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-run.c
@@ -28,12 +28,16 @@
     assert (as##TYPE[i] == 0 > VAL ? 0 : VAL);
 
 #define RUN_ALL()      \
+ RUN(int8_t, -1)       \
+ RUN(uint8_t, 2)       \
  RUN(int16_t, -1)      \
  RUN(uint16_t, 2)      \
  RUN(int32_t, -3)      \
  RUN(uint32_t, 4)      \
  RUN(int64_t, -5)      \
  RUN(uint64_t, 6)      \
+ RUN2(int8_t, -7)      \
+ RUN2(uint8_t, 8)      \
  RUN2(int16_t, -7)     \
  RUN2(uint16_t, 8)     \
  RUN2(int32_t, -9)     \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
index 46a321289fc460377f12fe2617e1b94f70dabdf7..7b217d990a68ba9ff9e884fe7e60af33b3ba25d5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c
@@ -3,5 +3,5 @@
 
 #include "vmax-template.h"
 
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
index 9bbaf76315791f263b1a72abb85fc9b7621bad42..1b7f8c6be166943601aa952ed2c2e3a4e2071045 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c
@@ -3,5 +3,5 @@
 
 #include "vmax-template.h"
 
-/* { dg-final { scan-assembler-times {\tvmax\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmax\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvmaxu\.vv} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h
index fc6a07e3ce9de16eaf161ba7c6e9ca956aa341a2..6deb5126c7d915c54b65db8db914c04c51860541 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmax-template.h
@@ -16,14 +16,17 @@
       dst[i] = a[i] > b ? a[i] : b;                    \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
  TEST_TYPE(uint32_t)   \
  TEST_TYPE(int64_t)    \
  TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int8_t)    \
+ TEST2_TYPE(uint8_t)   \
  TEST2_TYPE(int16_t)   \
  TEST2_TYPE(uint16_t)  \
  TEST2_TYPE(int32_t)   \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
index b461f8ba48443bcdc5fe25b8bace37c3a175913f..63c05a119a9afb48db54187e59737a5ede3d81c1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-run.c
@@ -28,12 +28,16 @@
     assert (as##TYPE[i] == 0 < VAL ? 0 : VAL);
 
 #define RUN_ALL()      \
+ RUN(int8_t, -1)       \
+ RUN(uint8_t, 2)       \
  RUN(int16_t, -1)      \
  RUN(uint16_t, 2)      \
  RUN(int32_t, -3)      \
  RUN(uint32_t, 4)      \
  RUN(int64_t, -5)      \
  RUN(uint64_t, 6)    \
+ RUN2(int8_t, -7)      \
+ RUN2(uint8_t, 8)      \
  RUN2(int16_t, -7)     \
  RUN2(uint16_t, 8)     \
  RUN2(int32_t, -9)     \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
index da3bb179ba77863baa4a33c897ab77da4024a084..bf826ebf53a3921ec1eb73a27965a9f227518810 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c
@@ -3,5 +3,5 @@
 
 #include "vmin-template.h"
 
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
index 07278b22b2d6294ef7e5fbb54952082109c550ea..f57d4369006ab951643c2b104790a5d7f6941f1b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c
@@ -3,5 +3,5 @@
 
 #include "vmin-template.h"
 
-/* { dg-final { scan-assembler-times {\tvmin\.vv} 6 } } */
-/* { dg-final { scan-assembler-times {\tvminu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmin\.vv} 8 } } */
+/* { dg-final { scan-assembler-times {\tvminu\.vv} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h
index 06f6b95461e27ef13c356e666436b1118a8b1a2d..1225d5aca64c63cebfa1efe4fad9bf51955801d4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmin-template.h
@@ -16,14 +16,17 @@
       dst[i] = a[i] < b ? a[i] : b;                    \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
  TEST_TYPE(uint32_t)   \
  TEST_TYPE(int64_t)    \
  TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int8_t)    \
+ TEST2_TYPE(uint8_t)   \
  TEST2_TYPE(int16_t)   \
  TEST2_TYPE(uint16_t)  \
  TEST2_TYPE(int32_t)   \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
index e8441c0605b02355c90cd8cc2cc4e5d55e067bb9..c560af9b85dd68091e6c7ce8f808b810e6ec1d6d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-run.c
@@ -15,7 +15,7 @@
     a##TYPE[i] = 2;                            \
     b##TYPE[i] = VAL;                          \
   }                                            \
-  vadd_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
+  vmul_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
   for (int i = 0; i < SZ; i++)                 \
     assert (a##TYPE[i] == 2 * VAL);
 
@@ -23,17 +23,21 @@
   TYPE as##TYPE[SZ];                           \
   for (int i = 0; i < SZ; i++)                 \
     as##TYPE[i] = 3;                           \
-  vadds_##TYPE (as##TYPE, as##TYPE, VAL, SZ);  \
+  vmuls_##TYPE (as##TYPE, as##TYPE, VAL, SZ);  \
   for (int i = 0; i < SZ; i++)                 \
     assert (as##TYPE[i] == 3 * VAL);
 
 #define RUN_ALL()      \
+ RUN(int8_t, -1)       \
+ RUN(uint8_t, 2)       \
  RUN(int16_t, -1)      \
  RUN(uint16_t, 2)      \
  RUN(int32_t, -3)      \
  RUN(uint32_t, 4)      \
  RUN(int64_t, -5)      \
  RUN(uint64_t, 6)      \
+ RUN2(int8_t, -7)      \
+ RUN2(uint8_t, 8)      \
  RUN2(int16_t, -7)     \
  RUN2(uint16_t, 8)     \
  RUN2(int32_t, -9)     \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
index f4df04d15ebf1f946533fa9525685e78e40f2cf1..53d920010da22e32ecf7301d13f0020a2024ebec 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c
@@ -3,4 +3,4 @@
 
 #include "vmul-template.h"
 
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
index f436b8a82a832bc25f35868be45e88601e1a568c..1624e16a53c5fc1bbe21faf88ec966c315e0cb0b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c
@@ -3,4 +3,4 @@
 
 #include "vmul-template.h"
 
-/* { dg-final { scan-assembler-times {\tvmul\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h
index 37f77972101dac2bcc00e7e1abec57a918d73612..33f9d87e1bb199edb01dae76a3e6f1d49bc41f6a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-template.h
@@ -2,7 +2,7 @@
 
 #define TEST_TYPE(TYPE)                                \
   __attribute__((noipa))                               \
-  void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)        \
+  void vmul_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n)        \
   {                                                    \
     for (int i = 0; i < n; i++)                                \
       dst[i] = a[i] * b[i];                            \
@@ -10,20 +10,23 @@
 
 #define TEST2_TYPE(TYPE)                               \
   __attribute__((noipa))                               \
-  void vadds_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)        \
+  void vmuls_##TYPE (TYPE *dst, TYPE *a, TYPE b, int n)        \
   {                                                    \
     for (int i = 0; i < n; i++)                                \
       dst[i] = a[i] * b;                               \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
  TEST_TYPE(uint32_t)   \
  TEST_TYPE(int64_t)    \
  TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int8_t)    \
+ TEST2_TYPE(uint8_t)   \
  TEST2_TYPE(int16_t)   \
  TEST2_TYPE(uint16_t)  \
  TEST2_TYPE(int32_t)   \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
index 5401e8d3ecdb140a41501f8d74cef33757787b88..f6b3770dcbb8a5159716dd67e92da645c686e7dc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-run.c
@@ -44,18 +44,24 @@
     assert (aim##TYPE[i] == (VAL | -16));
 
 #define RUN_ALL()      \
+ RUN(int8_t, -1)       \
+ RUN(uint8_t, 2)       \
  RUN(int16_t, -1)      \
  RUN(uint16_t, 2)      \
  RUN(int32_t, -3)      \
  RUN(uint32_t, 4)      \
  RUN(int64_t, -5)      \
  RUN(uint64_t, 6)      \
+ RUN2(int8_t, -7)      \
+ RUN2(uint8_t, 8)      \
  RUN2(int16_t, -7)     \
  RUN2(uint16_t, 8)     \
  RUN2(int32_t, -9)     \
  RUN2(uint32_t, 10)    \
  RUN2(int64_t, -11)    \
  RUN2(uint64_t, 12)    \
+ RUN3M(int8_t, 13)     \
+ RUN3(uint8_t, 14)     \
  RUN3M(int16_t, 13)    \
  RUN3(uint16_t, 14)    \
  RUN3M(int32_t, 15)    \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
index fc76d1c3b3e17a4f64608e494abbbc7645875230..70ea8ef65cc0293891c739b53e8f0cfcdc1d18fe 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c
@@ -3,5 +3,5 @@
 
 #include "vor-template.h"
 
-/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vi} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
index ae115a2f5039b4786f43e8bbb3a5d6e0fbcf54ea..44d09a2bddc9290a70d3b1a59cf56671ac7da9ab 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c
@@ -3,5 +3,5 @@
 
 #include "vor-template.h"
 
-/* { dg-final { scan-assembler-times {\tvor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvor\.vi} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h
index e60146cc232825a8769655e7aa5384b7d7d0e4bf..3daad2e889024b57a0e5f71ef69d1008c4d116a6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vor-template.h
@@ -32,20 +32,25 @@
       dst[i] = a[i] | -16;                             \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
  TEST_TYPE(uint32_t)   \
  TEST_TYPE(int64_t)    \
  TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int8_t)    \
+ TEST2_TYPE(uint8_t)   \
  TEST2_TYPE(int16_t)   \
  TEST2_TYPE(uint16_t)  \
  TEST2_TYPE(int32_t)   \
  TEST2_TYPE(uint32_t)  \
  TEST2_TYPE(int64_t)   \
  TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int8_t)   \
+ TEST3_TYPE(uint8_t)   \
  TEST3M_TYPE(int16_t)  \
  TEST3_TYPE(uint16_t)  \
  TEST3M_TYPE(int32_t)  \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
index 4a4c064e101a5be9fe7f9c77d8cac35026326791..58b69ec393e7e206765cf3b1f15f42963046fd0c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-run.c
@@ -28,12 +28,16 @@
     assert (as##TYPE[i] == 89 % VAL);
 
 #define RUN_ALL()      \
+ RUN(int8_t, -1)       \
+ RUN(uint8_t, 2)       \
  RUN(int16_t, -1)      \
  RUN(uint16_t, 2)      \
  RUN(int32_t, -3)      \
  RUN(uint32_t, 4)      \
  RUN(int64_t, -5)      \
  RUN(uint64_t, 6)      \
+ RUN2(int8_t, -7)      \
+ RUN2(uint8_t, 8)      \
  RUN2(int16_t, -7)     \
  RUN2(uint16_t, 8)     \
  RUN2(int32_t, -9)     \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
index df99f5019fb78a172e49c035181c510b6e2a9d86..7d2b478e1dea16b253476f5a0855d15ceae6392a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c
@@ -4,7 +4,7 @@
 #include "vrem-template.h"
 
 /* Currently we use an epilogue loop which also contains vrems.  Therefore we
-   expect 10 vrem[u]s instead of 6.  */
+   expect 14 vrem[u]s instead of 8.  */
 
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 14 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
index 3cff13a47e4afc29b444f19058d368680d69f3fa..b7bc1ccb86048d95832a725b37f337054cdb6309 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c
@@ -4,7 +4,7 @@
 #include "vrem-template.h"
 
 /* Currently we use an epilogue loop which also contains vrems.  Therefore we
-   expect 10 vrem[u]s instead of 6.  */
+   expect 14 vrem[u]s instead of 8.  */
 
-/* { dg-final { scan-assembler-times {\tvrem\.vv} 10 } } */
-/* { dg-final { scan-assembler-times {\tvremu\.vv} 10 } } */
+/* { dg-final { scan-assembler-times {\tvrem\.vv} 14 } } */
+/* { dg-final { scan-assembler-times {\tvremu\.vv} 14 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h
index d5ef40667ff8dd7223ee961413511d9b1e7b9d9d..9c4e6acae99d938a41c0b3da61993617881120f5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-template.h
@@ -16,14 +16,17 @@
       dst[i] = a[i] % b;                               \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
  TEST_TYPE(uint32_t)   \
  TEST_TYPE(int64_t)    \
  TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int8_t)    \
+ TEST2_TYPE(uint8_t)   \
  TEST2_TYPE(int16_t)   \
  TEST2_TYPE(uint16_t)  \
  TEST2_TYPE(int32_t)   \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
index 4f254872e33dba6230f8fb977124ee692b8319cc..fb6df757c905cd8055f6b50b992675b8ee449933 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-run.c
@@ -12,20 +12,20 @@
   TYPE b##TYPE[SZ];                            \
   for (int i = 0; i < SZ; i++)                 \
   {                                            \
-    a##TYPE[i] = 999;                          \
+    a##TYPE[i] = 123;                          \
     b##TYPE[i] = VAL;                          \
   }                                            \
   vsub_##TYPE (a##TYPE, a##TYPE, b##TYPE, SZ); \
   for (int i = 0; i < SZ; i++)                 \
-    assert (a##TYPE[i] == 999 - VAL);
+    assert (a##TYPE[i] == 123 - VAL);
 
 #define RUN2(TYPE,VAL)                         \
   TYPE as##TYPE[SZ];                           \
   for (int i = 0; i < SZ; i++)                 \
-    as##TYPE[i] = 999;                         \
+    as##TYPE[i] = 123;                         \
   vsubs_##TYPE (as##TYPE, as##TYPE, VAL, SZ);  \
   for (int i = 0; i < SZ; i++)                 \
-    assert (as##TYPE[i] == 999 - VAL);
+    assert (as##TYPE[i] == 123 - VAL);
 
 #define RUN3(TYPE)                             \
   TYPE as2##TYPE[SZ];                          \
@@ -44,24 +44,32 @@
     assert (as3##TYPE[i] == (TYPE)(15 - (i * -17 + 667)));
 
 #define RUN_ALL()      \
+ RUN(int8_t, 1)        \
+ RUN(uint8_t, 2)       \
  RUN(int16_t, 1)       \
  RUN(uint16_t, 2)      \
  RUN(int32_t, 3)       \
  RUN(uint32_t, 4)      \
  RUN(int64_t, 5)       \
  RUN(uint64_t, 6)      \
+ RUN2(int8_t, 7)       \
+ RUN2(uint8_t, 8)      \
  RUN2(int16_t, 7)      \
  RUN2(uint16_t, 8)     \
  RUN2(int32_t, 9)      \
  RUN2(uint32_t, 10)    \
  RUN2(int64_t, 11)     \
  RUN2(uint64_t, 12)    \
+ RUN3(int8_t)          \
+ RUN3(uint8_t)         \
  RUN3(int16_t)         \
  RUN3(uint16_t)                \
  RUN3(int32_t)         \
  RUN3(uint32_t)                \
  RUN3(int64_t)         \
  RUN3(uint64_t)                \
+ RUN4(int8_t)          \
+ RUN4(uint8_t)         \
  RUN4(int16_t)         \
  RUN4(uint16_t)                \
  RUN4(int32_t)         \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
index a0d3802be653a3786500e3c7cb2ea0018f3d5fb6..5641432410e91fb65e07233fa1493c95aef15956 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c
@@ -3,5 +3,5 @@
 
 #include "vsub-template.h"
 
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
index 562c026a7e4fa2deede9aec7259044943aaf33e2..4fe0969c3a0d2c795e9b6cd909f228b73f16dddc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c
@@ -3,5 +3,5 @@
 
 #include "vsub-template.h"
 
-/* { dg-final { scan-assembler-times {\tvsub\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvrsub\.vi} 12 } } */
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
index 47f07f134629524382cd17af0945ed004fd959e2..222972d47520e886a35e356ecdb4343c98d28768 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-template.h
@@ -32,26 +32,36 @@
       dst[i] = 15 - a[i];                              \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
  TEST_TYPE(uint32_t)   \
  TEST_TYPE(int64_t)    \
  TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int8_t)    \
+
+ TEST2_TYPE(uint8_t)   \
  TEST2_TYPE(int16_t)   \
  TEST2_TYPE(uint16_t)  \
  TEST2_TYPE(int32_t)   \
  TEST2_TYPE(uint32_t)  \
  TEST2_TYPE(int64_t)   \
  TEST2_TYPE(uint64_t)
+
+ TEST3_TYPE(int8_t)    \
+ TEST3_TYPE(uint8_t)   \
  TEST3_TYPE(int16_t)   \
  TEST3_TYPE(uint16_t)  \
  TEST3_TYPE(int32_t)   \
  TEST3_TYPE(uint32_t)  \
  TEST3_TYPE(int64_t)   \
  TEST3_TYPE(uint64_t)  \
+
+ TEST4_TYPE(int8_t)    \
+ TEST4_TYPE(uint8_t)   \
  TEST4_TYPE(int16_t)   \
  TEST4_TYPE(uint16_t)  \
  TEST4_TYPE(int32_t)   \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
index ab0975a6408ebf07630ee010fe6add93161ba59c..7239733d12cf92a496fe569fa2f6fbec162da11b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-run.c
@@ -44,18 +44,24 @@
     assert (aim##TYPE[i] == (VAL ^ -16));
 
 #define RUN_ALL()      \
+ RUN(int8_t, -1)       \
+ RUN(uint8_t, 2)       \
  RUN(int16_t, -1)      \
  RUN(uint16_t, 2)      \
  RUN(int32_t, -3)      \
  RUN(uint32_t, 4)      \
  RUN(int64_t, -5)      \
  RUN(uint64_t, 6)      \
+ RUN2(int8_t, -7)      \
+ RUN2(uint8_t, 8)      \
  RUN2(int16_t, -7)     \
  RUN2(uint16_t, 8)     \
  RUN2(int32_t, -9)     \
  RUN2(uint32_t, 10)    \
  RUN2(int64_t, -11)    \
  RUN2(uint64_t, 12)    \
+ RUN3M(int8_t, 13)     \
+ RUN3(uint8_t, 14)     \
  RUN3M(int16_t, 13)    \
  RUN3(uint16_t, 14)    \
  RUN3M(int32_t, 15)    \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
index fbef4a45770172c92629f65cb8bfaedbeb7cd1d1..83b223e987fe5a0b8c9dd9589dca6b809db440fb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c
@@ -3,5 +3,5 @@
 
 #include "vxor-template.h"
 
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vi} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
index 9729ad14eb13a668aa107389f3d805f271511a92..6ba007c9d90d8faa9a4114924d4473ac91217b03 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c
@@ -3,5 +3,5 @@
 
 #include "vxor-template.h"
 
-/* { dg-final { scan-assembler-times {\tvxor\.vv} 12 } } */
-/* { dg-final { scan-assembler-times {\tvxor\.vi} 6 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vv} 16 } } */
+/* { dg-final { scan-assembler-times {\tvxor\.vi} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h
index 370b242f19796325099a953834255def8a74b616..b36698b5311835f2a73a99c2d9b7abfb3a789b40 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vxor-template.h
@@ -32,20 +32,25 @@
       dst[i] = a[i] ^ -16;                             \
   }
 
-/* *int8_t not autovec currently. */
 #define TEST_ALL()     \
+ TEST_TYPE(int8_t)     \
+ TEST_TYPE(uint8_t)    \
  TEST_TYPE(int16_t)    \
  TEST_TYPE(uint16_t)   \
  TEST_TYPE(int32_t)    \
  TEST_TYPE(uint32_t)   \
  TEST_TYPE(int64_t)    \
  TEST_TYPE(uint64_t)    \
+ TEST2_TYPE(int8_t)    \
+ TEST2_TYPE(uint8_t)   \
  TEST2_TYPE(int16_t)   \
  TEST2_TYPE(uint16_t)  \
  TEST2_TYPE(int32_t)   \
  TEST2_TYPE(uint32_t)  \
  TEST2_TYPE(int64_t)   \
  TEST2_TYPE(uint64_t)   \
+ TEST3M_TYPE(int8_t)   \
+ TEST3_TYPE(uint8_t)   \
  TEST3M_TYPE(int16_t)  \
  TEST3_TYPE(uint16_t)  \
  TEST3M_TYPE(int32_t)  \