const struct intel_crtc_state *crtc_state)
{
u8 panel_replay_config[2];
+ u8 panel_replay_config_3;
panel_replay_config[0] = DP_PANEL_REPLAY_ENABLE |
DP_PANEL_REPLAY_VSC_SDP_CRC_EN |
DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN |
DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN;
panel_replay_config[1] = DP_PANEL_REPLAY_CRC_VERIFICATION;
-
if (crtc_state->has_sel_update)
panel_replay_config[0] |= DP_PANEL_REPLAY_SU_ENABLE;
drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG,
panel_replay_config, sizeof(panel_replay_config));
+
+ panel_replay_config_3 = intel_dp_as_sdp_transmission_time();
+ drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG3, panel_replay_config_3);
}
static void _psr_enable_sink(struct intel_dp *intel_dp,