]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amd/pm: Fetch ubb power for smu_v13_0_12
authorAsad Kamal <asad.kamal@amd.com>
Wed, 29 Oct 2025 13:14:44 +0000 (21:14 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 8 Dec 2025 18:56:33 +0000 (13:56 -0500)
Feth ubb power from system metrics table for smu_v13_0_12

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h

index 9e635f733fbfdf263a210bf803cdc0992c699289..07bee1f32f54f1512d851fa00c27096e37575157 100644 (file)
@@ -601,6 +601,40 @@ static bool smu_v13_0_12_is_temp_metrics_supported(struct smu_context *smu,
        return false;
 }
 
+int smu_v13_0_12_get_system_power(struct smu_context *smu,
+                                 enum amd_pp_sensors sensor,
+                                 uint32_t *value)
+{
+       struct smu_table_context *smu_table = &smu->smu_table;
+       struct smu_table *tables = smu_table->tables;
+       SystemMetricsTable_t *metrics;
+       struct smu_table *sys_table;
+       int ret;
+
+       if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SYSTEM_POWER_METRICS)))
+               return -EOPNOTSUPP;
+
+       ret = smu_v13_0_12_get_system_metrics_table(smu);
+       if (ret)
+               return ret;
+
+       sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS];
+       metrics = (SystemMetricsTable_t *)sys_table->cache.buffer;
+
+       switch (sensor) {
+       case AMDGPU_PP_SENSOR_UBB_POWER:
+               *value = metrics->SystemPower[SYSTEM_POWER_UBB_POWER];
+               break;
+       case AMDGPU_PP_SENSOR_UBB_POWER_LIMIT:
+               *value = metrics->SystemPower[SYSTEM_POWER_UBB_POWER_THRESHOLD];
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       return ret;
+}
+
 int smu_v13_0_12_get_npm_data(struct smu_context *smu,
                              enum amd_pp_sensors sensor,
                              uint32_t *value)
index 44e1cd821eec9abae229781cb53dec1ef0bc9f2d..2fefd258bc0e0fe1e74125b7d19893008c97ea7c 100644 (file)
@@ -1860,6 +1860,13 @@ static int smu_v13_0_6_read_sensor(struct smu_context *smu,
                        return ret;
                *size = 4;
                break;
+       case AMDGPU_PP_SENSOR_UBB_POWER:
+       case AMDGPU_PP_SENSOR_UBB_POWER_LIMIT:
+               ret = smu_v13_0_12_get_system_power(smu, sensor, (uint32_t *)data);
+               if (ret)
+                       return ret;
+               *size = 4;
+               break;
        case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
        default:
                ret = -EOPNOTSUPP;
index 6cbdd7c5ded9b3d12f848ef327ed680857f55a4c..0588a5aa952d65f05aaf99ef2336979e7968f023 100644 (file)
@@ -77,6 +77,7 @@ enum smu_v13_0_6_caps {
        SMU_CAP(NPM_METRICS),
        SMU_CAP(RAS_EEPROM),
        SMU_CAP(FAST_PPT),
+       SMU_CAP(SYSTEM_POWER_METRICS),
        SMU_CAP(ALL),
 };
 
@@ -107,6 +108,9 @@ void smu_v13_0_12_tables_fini(struct smu_context *smu);
 int smu_v13_0_12_get_npm_data(struct smu_context *smu,
                              enum amd_pp_sensors sensor,
                              uint32_t *value);
+int smu_v13_0_12_get_system_power(struct smu_context *smu,
+                                 enum amd_pp_sensors sensor,
+                                 uint32_t *value);
 extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[];
 extern const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[];
 extern const struct smu_temp_funcs smu_v13_0_12_temp_funcs;