Fix HChar / UCHar / Char mixups. VEX now compiles without

warnings about assigning pointers to incompatible types.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2550

diff --git a/VEX/priv/guest_amd64_helpers.c b/VEX/priv/guest_amd64_helpers.c
index 5f95e45dbbad9a153922d1b28615f19cd75ef061..4b3508b2f602831c22612e6e683a047f1bb6a09e 100644 (file)
--- a/VEX/priv/guest_amd64_helpers.c
+++ b/VEX/priv/guest_amd64_helpers.c
@@ -514,7 +514,7 @@ static UInt n_calc_cond = 0;
 static void showCounts ( void )
 {
    Int op, co;
-   Char ch;
+   HChar ch;
    vex_printf("\nTotal calls: calc_all=%u   calc_cond=%u   calc_c=%u\n",
               n_calc_all, n_calc_cond, n_calc_c);
 

diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c
index ed12a3e383c631f3f8a7d1f13646e9a7daa24075..7474802525744f5f1aa1197be33b3d9bb8dadff4 100644 (file)
--- a/VEX/priv/guest_amd64_toIR.c
+++ b/VEX/priv/guest_amd64_toIR.c
@@ -10773,7 +10773,7 @@ static Long dis_CVTDQ2PD_128 ( VexAbiInfo* vbi, Prefix pfx,
    UChar  modrm = getUChar(delta);
    IRTemp arg64 = newTemp(Ity_I64);
    UInt   rG    = gregOfRexRM(pfx,modrm);
-   UChar* mbV   = isAvx ? "v" : "";
+   HChar* mbV   = isAvx ? "v" : "";
    if (epartIsReg(modrm)) {
       UInt rE = eregOfRexRM(pfx,modrm);
       assign( arg64, getXMMRegLane64(rE, 0) );
@@ -15704,8 +15704,8 @@ static Long dis_PMOVxXBW_128 ( VexAbiInfo* vbi, Prefix pfx,
    HChar  dis_buf[50];
    IRTemp srcVec = newTemp(Ity_V128);
    UChar  modrm  = getUChar(delta);
-   UChar* mbV    = isAvx ? "v" : "";
-   UChar  how    = xIsZ ? 'z' : 's';
+   HChar* mbV    = isAvx ? "v" : "";
+   HChar  how    = xIsZ ? 'z' : 's';
    UInt   rG     = gregOfRexRM(pfx, modrm);
    if ( epartIsReg(modrm) ) {
       UInt rE = eregOfRexRM(pfx, modrm);
@@ -15746,8 +15746,8 @@ static Long dis_PMOVxXWD_128 ( VexAbiInfo* vbi, Prefix pfx,
    HChar  dis_buf[50];
    IRTemp srcVec = newTemp(Ity_V128);
    UChar  modrm  = getUChar(delta);
-   UChar* mbV    = isAvx ? "v" : "";
-   UChar  how    = xIsZ ? 'z' : 's';
+   HChar* mbV    = isAvx ? "v" : "";
+   HChar  how    = xIsZ ? 'z' : 's';
    UInt   rG     = gregOfRexRM(pfx, modrm);
 
    if ( epartIsReg(modrm) ) {
@@ -15785,7 +15785,7 @@ static Long dis_PMOVSXWQ_128 ( VexAbiInfo* vbi, Prefix pfx,
    HChar  dis_buf[50];
    IRTemp srcBytes = newTemp(Ity_I32);
    UChar  modrm    = getUChar(delta);
-   UChar* mbV      = isAvx ? "v" : "";
+   HChar* mbV      = isAvx ? "v" : "";
    UInt   rG       = gregOfRexRM(pfx, modrm);
 
    if ( epartIsReg( modrm ) ) {
@@ -15818,7 +15818,7 @@ static Long dis_PMOVZXWQ_128 ( VexAbiInfo* vbi, Prefix pfx,
    HChar  dis_buf[50];
    IRTemp srcVec = newTemp(Ity_V128);
    UChar  modrm    = getUChar(delta);
-   UChar* mbV      = isAvx ? "v" : "";
+   HChar* mbV      = isAvx ? "v" : "";
    UInt   rG       = gregOfRexRM(pfx, modrm);
 
    if ( epartIsReg( modrm ) ) {
@@ -15856,8 +15856,8 @@ static Long dis_PMOVxXDQ_128 ( VexAbiInfo* vbi, Prefix pfx,
    IRTemp srcI64 = newTemp(Ity_I64);
    IRTemp srcVec = newTemp(Ity_V128);
    UChar  modrm  = getUChar(delta);
-   UChar* mbV    = isAvx ? "v" : "";
-   UChar  how    = xIsZ ? 'z' : 's';
+   HChar* mbV    = isAvx ? "v" : "";
+   HChar  how    = xIsZ ? 'z' : 's';
    UInt   rG     = gregOfRexRM(pfx, modrm);
    /* Compute both srcI64 -- the value to expand -- and srcVec -- same
       thing in a V128, with arbitrary junk in the top 64 bits.  Use
@@ -15902,8 +15902,8 @@ static Long dis_PMOVxXBD_128 ( VexAbiInfo* vbi, Prefix pfx,
    HChar  dis_buf[50];
    IRTemp srcVec = newTemp(Ity_V128);
    UChar  modrm  = getUChar(delta);
-   UChar* mbV    = isAvx ? "v" : "";
-   UChar  how    = xIsZ ? 'z' : 's';
+   HChar* mbV    = isAvx ? "v" : "";
+   HChar  how    = xIsZ ? 'z' : 's';
    UInt   rG     = gregOfRexRM(pfx, modrm);
    if ( epartIsReg(modrm) ) {
       UInt rE = eregOfRexRM(pfx, modrm);
@@ -15945,7 +15945,7 @@ static Long dis_PMOVSXBQ_128 ( VexAbiInfo* vbi, Prefix pfx,
    HChar  dis_buf[50];
    IRTemp srcBytes = newTemp(Ity_I16);
    UChar  modrm    = getUChar(delta);
-   UChar* mbV      = isAvx ? "v" : "";
+   HChar* mbV      = isAvx ? "v" : "";
    UInt   rG       = gregOfRexRM(pfx, modrm);
    if ( epartIsReg(modrm) ) {
       UInt rE = eregOfRexRM(pfx, modrm);
@@ -15978,7 +15978,7 @@ static Long dis_PMOVZXBQ_128 ( VexAbiInfo* vbi, Prefix pfx,
    HChar  dis_buf[50];
    IRTemp srcVec   = newTemp(Ity_V128);
    UChar  modrm    = getUChar(delta);
-   UChar* mbV      = isAvx ? "v" : "";
+   HChar* mbV      = isAvx ? "v" : "";
    UInt   rG       = gregOfRexRM(pfx, modrm);
    if ( epartIsReg(modrm) ) {
       UInt rE = eregOfRexRM(pfx, modrm);
@@ -16015,7 +16015,7 @@ static Long dis_PHMINPOSUW_128 ( VexAbiInfo* vbi, Prefix pfx,
    Int    alen   = 0;
    HChar  dis_buf[50];
    UChar  modrm  = getUChar(delta);
-   UChar* mbV    = isAvx ? "v" : "";
+   HChar* mbV    = isAvx ? "v" : "";
    IRTemp sV     = newTemp(Ity_V128);
    IRTemp sHi    = newTemp(Ity_I64);
    IRTemp sLo    = newTemp(Ity_I64);
@@ -17120,7 +17120,7 @@ static Long dis_PEXTRB_128_GtoE ( VexAbiInfo* vbi, Prefix pfx,
    IRTemp xmm_vec  = newTemp(Ity_V128);
    IRTemp sel_lane = newTemp(Ity_I32);
    IRTemp shr_lane = newTemp(Ity_I32);
-   UChar* mbV      = isAvx ? "v" : "";
+   HChar* mbV      = isAvx ? "v" : "";
    UChar  modrm    = getUChar(delta);
    IRTemp t3, t2, t1, t0;
    Int    imm8;
@@ -23164,7 +23164,7 @@ Long dis_ESC_0F__VEX (
          UInt   rD    = gregOfRexRM(pfx, modrm);
          IRTemp tD    = newTemp(Ity_V256);
          Bool   isA   = have66noF2noF3(pfx);
-         UChar  ch    = isA ? 'a' : 'u';
+         HChar  ch    = isA ? 'a' : 'u';
          if (epartIsReg(modrm)) {
             UInt rS = eregOfRexRM(pfx, modrm);
             delta += 1;
@@ -23189,7 +23189,7 @@ Long dis_ESC_0F__VEX (
          UInt   rD    = gregOfRexRM(pfx, modrm);
          IRTemp tD    = newTemp(Ity_V128);
          Bool   isA   = have66noF2noF3(pfx);
-         UChar  ch    = isA ? 'a' : 'u';
+         HChar  ch    = isA ? 'a' : 'u';
          if (epartIsReg(modrm)) {
             UInt rS = eregOfRexRM(pfx, modrm);
             delta += 1;
@@ -23590,7 +23590,7 @@ Long dis_ESC_0F__VEX (
          UInt   rS    = gregOfRexRM(pfx, modrm);
          IRTemp tS    = newTemp(Ity_V256);
          Bool   isA   = have66noF2noF3(pfx);
-         UChar  ch    = isA ? 'a' : 'u';
+         HChar  ch    = isA ? 'a' : 'u';
          assign(tS, getYMMReg(rS));
          if (epartIsReg(modrm)) {
             UInt rD = eregOfRexRM(pfx, modrm);
@@ -23615,7 +23615,7 @@ Long dis_ESC_0F__VEX (
          UInt   rS    = gregOfRexRM(pfx, modrm);
          IRTemp tS    = newTemp(Ity_V128);
          Bool   isA   = have66noF2noF3(pfx);
-         UChar  ch    = isA ? 'a' : 'u';
+         HChar  ch    = isA ? 'a' : 'u';
          assign(tS, getXMMReg(rS));
          if (epartIsReg(modrm)) {
             UInt rD = eregOfRexRM(pfx, modrm);
@@ -24597,7 +24597,7 @@ Long dis_ESC_0F38__VEX (
          IRTemp dV      = newTemp(Ity_V128);
          IRTemp sHi, sLo, dHi, dLo;
          sHi = sLo = dHi = dLo = IRTemp_INVALID;
-         UChar  ch      = '?';
+         HChar  ch      = '?';
          Int    laneszB = 0;
          UChar  modrm   = getUChar(delta);
          UInt   rG      = gregOfRexRM(pfx,modrm);

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index 34b925d22d64ad7a1ff874ff4ec931ad6506cebe..5f5a0c8cbc9f34b196c5ba6ccc7c98f618771018 100644 (file)
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -2383,7 +2383,7 @@ IRExpr* mk_EA_reg_plusminus_imm12 ( UInt rN, UInt bU, UInt imm12,
    vassert(rN < 16);
    vassert(bU < 2);
    vassert(imm12 < 0x1000);
-   UChar opChar = bU == 1 ? '+' : '-';
+   HChar opChar = bU == 1 ? '+' : '-';
    DIS(buf, "[r%u, #%c%u]", rN, opChar, imm12);
    return
       binop( (bU == 1 ? Iop_Add32 : Iop_Sub32),
@@ -2405,7 +2405,7 @@ IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM,
    vassert(rM < 16);
    vassert(sh2 < 4);
    vassert(imm5 < 32);
-   UChar   opChar = bU == 1 ? '+' : '-';
+   HChar   opChar = bU == 1 ? '+' : '-';
    IRExpr* index  = NULL;
    switch (sh2) {
       case 0: /* LSL */
@@ -2472,7 +2472,7 @@ IRExpr* mk_EA_reg_plusminus_imm8 ( UInt rN, UInt bU, UInt imm8,
    vassert(rN < 16);
    vassert(bU < 2);
    vassert(imm8 < 0x100);
-   UChar opChar = bU == 1 ? '+' : '-';
+   HChar opChar = bU == 1 ? '+' : '-';
    DIS(buf, "[r%u, #%c%u]", rN, opChar, imm8);
    return
       binop( (bU == 1 ? Iop_Add32 : Iop_Sub32),
@@ -2489,7 +2489,7 @@ IRExpr* mk_EA_reg_plusminus_reg ( UInt rN, UInt bU, UInt rM,
    vassert(rN < 16);
    vassert(bU < 2);
    vassert(rM < 16);
-   UChar   opChar = bU == 1 ? '+' : '-';
+   HChar   opChar = bU == 1 ? '+' : '-';
    IRExpr* index  = getIRegA(rM);
    DIS(buf, "[r%u, %c r%u]", rN, opChar, rM); 
    return binop(bU == 1 ? Iop_Add32 : Iop_Sub32,
@@ -2644,9 +2644,9 @@ static UInt thumbExpandImm_from_I0_I1 ( Bool* updatesC,
    block are tagged with a 1 bit.
 */
 static Bool compute_ITSTATE ( /*OUT*/UInt*  itstate,
-                              /*OUT*/UChar* ch1,
-                              /*OUT*/UChar* ch2,
-                              /*OUT*/UChar* ch3,
+                              /*OUT*/HChar* ch1,
+                              /*OUT*/HChar* ch2,
+                              /*OUT*/HChar* ch3,
                               UInt firstcond, UInt mask )
 {
    vassert(firstcond <= 0xF);
@@ -3061,7 +3061,7 @@ Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT )
             IROp addOp;
             IROp andOp;
             IROp shOp;
-            char regType = Q ? 'q' : 'd';
+            HChar regType = Q ? 'q' : 'd';
 
             if (size == 3)
                return False;
@@ -3130,7 +3130,7 @@ Bool dis_neon_data_3same ( UInt theInstr, IRTemp condT )
             /* VQADD */
             IROp op, op2;
             IRTemp tmp;
-            char reg_t = Q ? 'q' : 'd';
+            HChar reg_t = Q ? 'q' : 'd';
             if (Q) {
                switch (size) {
                   case 0:
@@ -15715,9 +15715,9 @@ DisResult disInstr_THUMB_WRK (
       UInt newITSTATE = 0;
       /* This is the ITSTATE represented as described in
          libvex_guest_arm.h.  It is not the ARM ARM representation. */
-      UChar c1 = '.';
-      UChar c2 = '.';
-      UChar c3 = '.';
+      HChar c1 = '.';
+      HChar c2 = '.';
+      HChar c3 = '.';
       Bool valid = compute_ITSTATE( &newITSTATE, &c1, &c2, &c3,
                                     firstcond, mask );
       if (valid && firstcond != 0xF/*NV*/) {

diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index f7d8d0f7a73231bd72b32eb19697c559d53ad95e..800f8ef95f8ef3d8fef38fc3defcebe934772edd 100644 (file)
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -12089,7 +12089,7 @@ dis_vxv_dp_arith ( UInt theInstr, UInt opc2 )
       case 0x1A0: // xvsubdp (VSX Vector Subtract Double-Precision)
       {
          IROp mOp;
-         Char * oper_name;
+         HChar * oper_name;
          switch (opc2) {
             case 0x1E0:
                mOp = Iop_DivF64;
@@ -12158,7 +12158,7 @@ dis_vxv_dp_arith ( UInt theInstr, UInt opc2 )
           */
          Bool negate;
          IROp mOp = Iop_INVALID;
-         Char * oper_name = NULL;
+         HChar * oper_name = NULL;
          Bool mdp = False;
 
          switch (opc2) {
@@ -12420,7 +12420,7 @@ dis_vxv_sp_arith ( UInt theInstr, UInt opc2 )
          IRTemp t3, t2, t1, t0;
          Bool msp = False;
          Bool negate;
-         Char * oper_name = NULL;
+         HChar * oper_name = NULL;
          IROp mOp = Iop_INVALID;
          switch (opc2) {
             case 0x104: case 0x124:
@@ -12811,7 +12811,7 @@ static IRExpr * get_max_min_fp(IRTemp frA_I64, IRTemp frB_I64, Bool isMin)
 /*
  * Helper function for vector/scalar double precision fp round to integer instructions.
  */
-static IRExpr * _do_vsx_fp_roundToInt(IRTemp frB_I64, UInt opc2, UChar * insn_suffix)
+static IRExpr * _do_vsx_fp_roundToInt(IRTemp frB_I64, UInt opc2, HChar * insn_suffix)
 {
 
    /* The same rules apply for x{s|v}rdpi{m|p|c|z} as for floating point round operations (fri{m|n|p|z}). */
@@ -13271,7 +13271,7 @@ dis_vxv_misc ( UInt theInstr, UInt opc2 )
          IRTemp frBLo_I64 = newTemp(Ity_I64);
          IRExpr * frD_fp_roundHi = NULL;
          IRExpr * frD_fp_roundLo = NULL;
-         UChar * insn_suffix = NULL;
+         HChar * insn_suffix = NULL;
 
          assign( frBHi_I64, unop( Iop_V128HIto64, getVSReg( XB ) ) );
          frD_fp_roundHi = _do_vsx_fp_roundToInt(frBHi_I64, opc2, insn_suffix);
@@ -13291,7 +13291,7 @@ dis_vxv_misc ( UInt theInstr, UInt opc2 )
       case 0x152: // xvrspip (VSX Vector Round to SinglePrecision Integer using round toward +Infinity)
       case 0x132: // xvrspiz (VSX Vector Round to SinglePrecision Integer using round toward Zero)
       {
-         UChar * insn_suffix = NULL;
+         HChar * insn_suffix = NULL;
          IROp op;
          if (opc2 != 0x156) {
             // Use pre-defined IRop's for vrfi{m|n|p|z}
@@ -13880,7 +13880,7 @@ dis_vxs_misc( UInt theInstr, UInt opc2 )
       {
          IRTemp frB_I64 = newTemp(Ity_I64);
          IRExpr * frD_fp_round = NULL;
-         UChar * insn_suffix = NULL;
+         HChar * insn_suffix = NULL;
 
          assign(frB_I64, unop(Iop_V128HIto64, mkexpr( vB )));
          frD_fp_round = _do_vsx_fp_roundToInt(frB_I64, opc2, insn_suffix);
@@ -14218,7 +14218,7 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 )
       case 0x48: // xxmrghw (VSX Merge High Word)
       case 0xc8: // xxmrglw (VSX Merge Low Word)
       {
-         char type = (opc2 == 0x48) ? 'h' : 'l';
+         HChar type = (opc2 == 0x48) ? 'h' : 'l';
          IROp word_op = (opc2 == 0x48) ? Iop_V128HIto64 : Iop_V128to64;
          IRTemp a64 = newTemp(Ity_I64);
          IRTemp ahi32 = newTemp(Ity_I32);
@@ -16273,7 +16273,7 @@ static Bool dis_av_fp_convert ( UInt theInstr )
 
 struct vsx_insn {
    UInt opcode;
-   Char * name;
+   HChar * name;
 };
 
 //  ATTENTION:  Keep this array sorted on the opcocde!!!

diff --git a/VEX/priv/guest_x86_helpers.c b/VEX/priv/guest_x86_helpers.c
index 1a6f89417bba420a8045df4e0d1d8ea8530d7c75..1ae1d3cf132b4f29330a4dc6e1bc6cf1459fe114 100644 (file)
--- a/VEX/priv/guest_x86_helpers.c
+++ b/VEX/priv/guest_x86_helpers.c
@@ -436,7 +436,7 @@ static UInt n_calc_cond = 0;
 static void showCounts ( void )
 {
    Int op, co;
-   Char ch;
+   HChar ch;
    vex_printf("\nTotal calls: calc_all=%u   calc_cond=%u   calc_c=%u\n",
               n_calc_all, n_calc_cond, n_calc_c);
 

diff --git a/VEX/priv/host_mips_defs.c b/VEX/priv/host_mips_defs.c
index 590372aa0a8732011c4f4b65b1e107a5d07140e4..02f396799e875066655f4133ac02b1260b2e17ca 100644 (file)
--- a/VEX/priv/host_mips_defs.c
+++ b/VEX/priv/host_mips_defs.c
@@ -1648,7 +1648,7 @@ void ppMIPSInstr(MIPSInstr * i, Bool mode64)
       case Min_Load: {
          Bool idxd = toBool(i->Min.Load.src->tag == Mam_RR);
          UChar sz = i->Min.Load.sz;
-         UChar c_sz = sz == 1 ? 'b' : sz == 2 ? 'h' : sz == 4 ? 'w' : 'd';
+         HChar c_sz = sz == 1 ? 'b' : sz == 2 ? 'h' : sz == 4 ? 'w' : 'd';
          vex_printf("l%c%s ", c_sz, idxd ? "x" : "");
          ppHRegMIPS(i->Min.Load.dst, mode64);
          vex_printf(",");
@@ -1658,7 +1658,7 @@ void ppMIPSInstr(MIPSInstr * i, Bool mode64)
       case Min_Store: {
          UChar sz = i->Min.Store.sz;
          Bool idxd = toBool(i->Min.Store.dst->tag == Mam_RR);
-         UChar c_sz = sz == 1 ? 'b' : sz == 2 ? 'h' : sz == 4 ? 'w' : 'd';
+         HChar c_sz = sz == 1 ? 'b' : sz == 2 ? 'h' : sz == 4 ? 'w' : 'd';
          vex_printf("s%c%s ", c_sz, idxd ? "x" : "");
          ppHRegMIPS(i->Min.Store.src, mode64);
          vex_printf(",");

diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c
index 44c23ba608cac56aad7500c86f0c8e5fe9ef9b93..52f84efb483b0d492912b50b91833e6c621bbfb6 100644 (file)
--- a/VEX/priv/host_ppc_defs.c
+++ b/VEX/priv/host_ppc_defs.c
@@ -1624,7 +1624,7 @@ void ppPPCInstr ( PPCInstr* i, Bool mode64 )
    case Pin_Load: {
       Bool idxd = toBool(i->Pin.Load.src->tag == Pam_RR);
       UChar sz = i->Pin.Load.sz;
-      UChar c_sz = sz==1 ? 'b' : sz==2 ? 'h' : sz==4 ? 'w' : 'd';
+      HChar c_sz = sz==1 ? 'b' : sz==2 ? 'h' : sz==4 ? 'w' : 'd';
       vex_printf("l%c%s%s ", c_sz, sz==8 ? "" : "z", idxd ? "x" : "" );
       ppHRegPPC(i->Pin.Load.dst);
       vex_printf(",");
@@ -1640,7 +1640,7 @@ void ppPPCInstr ( PPCInstr* i, Bool mode64 )
    case Pin_Store: {
       UChar sz = i->Pin.Store.sz;
       Bool idxd = toBool(i->Pin.Store.dst->tag == Pam_RR);
-      UChar c_sz = sz==1 ? 'b' : sz==2 ? 'h' : sz==4 ? 'w' : /*8*/ 'd';
+      HChar c_sz = sz==1 ? 'b' : sz==2 ? 'h' : sz==4 ? 'w' : /*8*/ 'd';
       vex_printf("st%c%s ", c_sz, idxd ? "x" : "" );
       ppHRegPPC(i->Pin.Store.src);
       vex_printf(",");
@@ -1927,7 +1927,7 @@ void ppPPCInstr ( PPCInstr* i, Bool mode64 )
 
    case Pin_AvSplat: {
       UChar sz = i->Pin.AvSplat.sz;
-      UChar ch_sz = toUChar( (sz == 8) ? 'b' : (sz == 16) ? 'h' : 'w' );
+      HChar ch_sz = toUChar( (sz == 8) ? 'b' : (sz == 16) ? 'h' : 'w' );
       vex_printf("vsplt%s%c ",
                  i->Pin.AvSplat.src->tag == Pvi_Imm ? "is" : "", ch_sz);
       ppHRegPPC(i->Pin.AvSplat.dst);