phy: qcom: qmp-combo: Add new PHY sequences for SM8750

Add new register offsets and PHY values for SM8750. Some of the previous
definitions can be leveraged from older PHY versions as offsets within
registers have not changed. This also adds the required PHY sequence that
is recommended after running hardware characterization.

Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Signed-off-by: Melody Olvera <melody.olvera@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250527-sm8750_usb_master-v6-4-d58de3b41d34@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index b09fa00e9fe7db8d97b7179ee15d3f07fe578b0c..8b9710a9654ab1acf8419e7f87188cbc98f8714a 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -32,6 +32,7 @@
 #include "phy-qcom-qmp-pcs-usb-v4.h"
 #include "phy-qcom-qmp-pcs-usb-v5.h"
 #include "phy-qcom-qmp-pcs-usb-v6.h"
+#include "phy-qcom-qmp-pcs-usb-v8.h"
 
 #include "phy-qcom-qmp-dp-com-v3.h"
 
@@ -212,6 +213,28 @@ static const unsigned int qmp_v6_n4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
        [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN,
 };
 
+static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
+       [QPHY_SW_RESET]                 = QPHY_V8_PCS_SW_RESET,
+       [QPHY_START_CTRL]               = QPHY_V8_PCS_START_CONTROL,
+       [QPHY_PCS_STATUS]               = QPHY_V8_PCS_PCS_STATUS1,
+       [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V8_PCS_POWER_DOWN_CONTROL,
+
+       /* In PCS_USB */
+       [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL,
+       [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR,
+
+       [QPHY_COM_RESETSM_CNTRL]        = QSERDES_V8_COM_RESETSM_CNTRL,
+       [QPHY_COM_C_READY_STATUS]       = QSERDES_V8_COM_C_READY_STATUS,
+       [QPHY_COM_CMN_STATUS]           = QSERDES_V8_COM_CMN_STATUS,
+       [QPHY_COM_BIAS_EN_CLKBUFLR_EN]  = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN,
+
+       [QPHY_TX_TX_POL_INV]            = QSERDES_V8_TX_TX_POL_INV,
+       [QPHY_TX_TX_DRV_LVL]            = QSERDES_V8_TX_TX_DRV_LVL,
+       [QPHY_TX_TX_EMP_POST1_LVL]      = QSERDES_V8_TX_TX_EMP_POST1_LVL,
+       [QPHY_TX_HIGHZ_DRVR_EN]         = QSERDES_V8_TX_HIGHZ_DRVR_EN,
+       [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V8_TX_TRANSCEIVER_BIAS_EN,
+};
+
 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
        QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
        QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
@@ -1471,6 +1494,139 @@ static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = {
        QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10),
 };
 
+static const struct qmp_phy_init_tbl sm8750_usb3_serdes_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x02),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x16),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x36),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORECLK_DIV_MODE1, 0x04),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x16),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x41),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x41),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE1, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE1, 0x55),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE1, 0x75),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE1, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE1, 0x25),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE1, 0x02),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x02),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x16),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x36),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x08),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x1a),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE0, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE0, 0x55),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE0, 0x75),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE0, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE0, 0x25),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE0, 0x02),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_BG_TIMER, 0x0a),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_EN_CENTER, 0x01),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER1, 0x62),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER2, 0x02),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_BUF_ENABLE, 0x0c),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0x1a),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x14),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORE_CLK_EN, 0x20),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36),
+       QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADDITIONAL_MISC, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl sm8750_usb3_tx_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_TX, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_RX, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
+       QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
+       QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_1, 0xf5),
+       QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_3, 0x11),
+       QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_4, 0x31),
+       QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_5, 0x5f),
+       QMP_PHY_INIT_CFG(QSERDES_V8_TX_RCV_DETECT_LVL_2, 0x12),
+       QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x21, 1),
+       QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x05, 2),
+};
+
+static const struct qmp_phy_init_tbl sm8750_usb3_rx_tbl[] = {
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FO_GAIN, 0x0a),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_GAIN, 0x06),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_PI_CONTROLS, 0x99),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH1, 0x08),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH2, 0x08),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN1, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN2, 0x0a),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE, 0x20),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL1, 0x54),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL2, 0x0f),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_GM_CAL, 0x13),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW, 0x07),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
+
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_ENABLES, 0x0c),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CNTRL, 0x04),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_LOW, 0x3f),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH, 0xbf),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH2, 0xff),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH3, 0xdf),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH4, 0xed),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_LOW, 0x19),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH, 0x09),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH2, 0x91),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH3, 0xb7),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH4, 0xaa),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_EN_TIMER, 0x04),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_DCC_CTRL1, 0x0c),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_VTH_CODE, 0x10),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_CTRL1, 0x14),
+       QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_TRIM, 0x08),
+};
+
+static const struct qmp_phy_init_tbl sm8750_usb3_pcs_tbl[] = {
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG1, 0xc4),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG2, 0x89),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG3, 0x20),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG6, 0x13),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_REFGEN_REQ_CONFIG1, 0x21),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_RX_SIGDET_LVL, 0x55),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_CDR_RESET_TIME, 0x0a),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG1, 0x88),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG2, 0x13),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_PCS_TX_RX_CONFIG, 0x0c),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG1, 0x4b),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG5, 0x10),
+};
+
+static const struct qmp_phy_init_tbl sm8750_usb3_pcs_usb_tbl[] = {
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L, 0x40),
+       QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H, 0x00),
+};
+
 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = {
        QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
        QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
@@ -1781,6 +1937,22 @@ static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
        .dp_dp_phy      = 0x2200,
 };
 
+static const struct qmp_combo_offsets qmp_combo_offsets_v8 = {
+       .com            = 0x0000,
+       .txa            = 0x1400,
+       .rxa            = 0x1600,
+       .txb            = 0x1800,
+       .rxb            = 0x1a00,
+       .usb3_serdes    = 0x1000,
+       .usb3_pcs_misc  = 0x1c00,
+       .usb3_pcs       = 0x1e00,
+       .usb3_pcs_usb   = 0x2100,
+       .dp_serdes      = 0x3000,
+       .dp_txa         = 0x3400,
+       .dp_txb         = 0x3800,
+       .dp_dp_phy      = 0x3c00,
+};
+
 static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = {
        .offsets                = &qmp_combo_offsets_v3,
 
@@ -2280,6 +2452,51 @@ static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg = {
        .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
 };
 
+static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg = {
+       .offsets                = &qmp_combo_offsets_v8,
+
+       .serdes_tbl             = sm8750_usb3_serdes_tbl,
+       .serdes_tbl_num         = ARRAY_SIZE(sm8750_usb3_serdes_tbl),
+       .tx_tbl                 = sm8750_usb3_tx_tbl,
+       .tx_tbl_num             = ARRAY_SIZE(sm8750_usb3_tx_tbl),
+       .rx_tbl                 = sm8750_usb3_rx_tbl,
+       .rx_tbl_num             = ARRAY_SIZE(sm8750_usb3_rx_tbl),
+       .pcs_tbl                = sm8750_usb3_pcs_tbl,
+       .pcs_tbl_num            = ARRAY_SIZE(sm8750_usb3_pcs_tbl),
+       .pcs_usb_tbl            = sm8750_usb3_pcs_usb_tbl,
+       .pcs_usb_tbl_num        = ARRAY_SIZE(sm8750_usb3_pcs_usb_tbl),
+
+       .dp_serdes_tbl          = qmp_v6_dp_serdes_tbl,
+       .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
+       .dp_tx_tbl              = qmp_v6_dp_tx_tbl,
+       .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
+
+       .serdes_tbl_rbr         = qmp_v6_dp_serdes_tbl_rbr,
+       .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
+       .serdes_tbl_hbr         = qmp_v6_dp_serdes_tbl_hbr,
+       .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
+       .serdes_tbl_hbr2        = qmp_v6_dp_serdes_tbl_hbr2,
+       .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
+       .serdes_tbl_hbr3        = qmp_v6_dp_serdes_tbl_hbr3,
+       .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
+
+       .swing_hbr_rbr          = &qmp_dp_v6_voltage_swing_hbr_rbr,
+       .pre_emphasis_hbr_rbr   = &qmp_dp_v6_pre_emphasis_hbr_rbr,
+       .swing_hbr3_hbr2        = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
+       .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
+
+       .dp_aux_init            = qmp_v4_dp_aux_init,
+       .configure_dp_tx        = qmp_v4_configure_dp_tx,
+       .configure_dp_phy       = qmp_v4_configure_dp_phy,
+       .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
+
+       .regs                   = qmp_v8_usb3phy_regs_layout,
+       .reset_list             = msm8996_usb3phy_reset_l,
+       .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+       .vreg_list              = qmp_phy_vreg_l,
+       .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
+};
+
 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp)
 {
        const struct qmp_phy_cfg *cfg = qmp->cfg;
@@ -3915,6 +4132,10 @@ static const struct of_device_id qmp_combo_of_match_table[] = {
                .compatible = "qcom,sm8650-qmp-usb3-dp-phy",
                .data = &sm8650_usb3dpphy_cfg,
        },
+       {
+               .compatible = "qcom,sm8750-qmp-usb3-dp-phy",
+               .data = &sm8750_usb3dpphy_cfg,
+       },
        {
                .compatible = "qcom,x1e80100-qmp-usb3-dp-phy",
                .data = &x1e80100_usb3dpphy_cfg,

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v8.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v8.h
new file mode 100644 (file)
index 0000000..89ace80
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v8.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_USB_V8_H_
+#define QCOM_PHY_QMP_PCS_USB_V8_H_
+
+#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG1            0x00
+#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_STATUS         0x04
+#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL           0x08
+#define QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL2          0x0c
+#define QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_SOURCE_STATUS  0x10
+#define QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR          0x14
+#define QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL                0x18
+#define QPHY_V8_PCS_USB_LFPS_TX_ECSTART                        0x1c
+#define QPHY_V8_PCS_USB_LFPS_PER_TIMER_VAL             0x20
+#define QPHY_V8_PCS_USB_LFPS_TX_END_CNT_U3_START       0x24
+#define QPHY_V8_PCS_USB_LFPS_CONFIG1                   0x28
+#define QPHY_V8_PCS_USB_RXEQTRAINING_LOCK_TIME         0x2c
+#define QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME         0x30
+#define QPHY_V8_PCS_USB_RXEQTRAINING_CTLE_TIME         0x34
+#define QPHY_V8_PCS_USB_RXEQTRAINING_WAIT_TIME_S2      0x38
+#define QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2       0x3c
+#define QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L             0x40
+#define QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H             0x44
+#define QPHY_V8_PCS_USB_ARCVR_DTCT_EN_PERIOD           0x48
+#define QPHY_V8_PCS_USB_ARCVR_DTCT_CM_DLY              0x4c
+#define QPHY_V8_PCS_USB_TXONESZEROS_RUN_LENGTH         0x50
+#define QPHY_V8_PCS_USB_ALFPS_DEGLITCH_VAL             0x54
+#define QPHY_V8_PCS_USB_SIGDET_STARTUP_TIMER_VAL       0x58
+#define QPHY_V8_PCS_USB_TEST_CONTROL                   0x5c
+#define QPHY_V8_PCS_USB_RXTERMINATION_DLY_SEL          0x60
+#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG2            0x64
+#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG3            0x68
+#define QPHY_V8_PCS_USB_POWER_STATE_CONFIG4            0x6c
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8.h
new file mode 100644 (file)
index 0000000..169fd5d
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v8.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V8_H_
+#define QCOM_PHY_QMP_PCS_V8_H_
+
+/* Only for QMP V8 PHY - USB/PCIe PCS registers */
+#define QPHY_V8_PCS_SW_RESET                   0x000
+#define QPHY_V8_PCS_PCS_STATUS1                        0x014
+#define QPHY_V8_PCS_POWER_DOWN_CONTROL         0x040
+#define QPHY_V8_PCS_START_CONTROL              0x044
+#define QPHY_V8_PCS_POWER_STATE_CONFIG1                0x090
+#define QPHY_V8_PCS_LOCK_DETECT_CONFIG1                0x0c4
+#define QPHY_V8_PCS_LOCK_DETECT_CONFIG2                0x0c8
+#define QPHY_V8_PCS_LOCK_DETECT_CONFIG3                0x0cc
+#define QPHY_V8_PCS_LOCK_DETECT_CONFIG6                0x0d8
+#define QPHY_V8_PCS_REFGEN_REQ_CONFIG1         0x0dc
+#define QPHY_V8_PCS_RX_SIGDET_LVL              0x188
+#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L       0x190
+#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H       0x194
+#define QPHY_V8_PCS_RATE_SLEW_CNTRL1           0x198
+#define QPHY_V8_PCS_CDR_RESET_TIME             0x1b0
+#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG1       0x1c0
+#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG2       0x1c4
+#define QPHY_V8_PCS_PCS_TX_RX_CONFIG           0x1d0
+#define QPHY_V8_PCS_EQ_CONFIG1                 0x1dc
+#define QPHY_V8_PCS_EQ_CONFIG2                 0x1e0
+#define QPHY_V8_PCS_EQ_CONFIG5                 0x1ec
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h
new file mode 100644 (file)
index 0000000..d3b2292
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_COM_V8_H_
+#define QCOM_PHY_QMP_QSERDES_COM_V8_H_
+
+/* Only for QMP V8 PHY - QSERDES COM registers */
+#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1            0x000
+#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1            0x004
+#define QSERDES_V8_COM_SSC_STEP_SIZE3_MODE1            0x008
+#define QSERDES_V8_COM_CP_CTRL_MODE1                   0x010
+#define QSERDES_V8_COM_PLL_RCTRL_MODE1                 0x014
+#define QSERDES_V8_COM_PLL_CCTRL_MODE1                 0x018
+#define QSERDES_V8_COM_CORECLK_DIV_MODE1               0x01c
+#define QSERDES_V8_COM_LOCK_CMP1_MODE1                 0x020
+#define QSERDES_V8_COM_LOCK_CMP2_MODE1                 0x024
+#define QSERDES_V8_COM_DEC_START_MODE1                 0x028
+#define QSERDES_V8_COM_DEC_START_MSB_MODE1             0x02c
+#define QSERDES_V8_COM_DIV_FRAC_START1_MODE1           0x030
+#define QSERDES_V8_COM_DIV_FRAC_START2_MODE1           0x034
+#define QSERDES_V8_COM_DIV_FRAC_START3_MODE1           0x038
+#define QSERDES_V8_COM_HSCLK_SEL_1                     0x03c
+#define QSERDES_V8_COM_VCO_TUNE1_MODE1                 0x048
+#define QSERDES_V8_COM_VCO_TUNE2_MODE1                 0x04c
+#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1      0x050
+#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1      0x054
+#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0      0x058
+#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0      0x05c
+#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0            0x060
+#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0            0x064
+#define QSERDES_V8_COM_CP_CTRL_MODE0                   0x070
+#define QSERDES_V8_COM_PLL_RCTRL_MODE0                 0x074
+#define QSERDES_V8_COM_PLL_CCTRL_MODE0                 0x078
+#define QSERDES_V8_COM_LOCK_CMP1_MODE0                 0x080
+#define QSERDES_V8_COM_LOCK_CMP2_MODE0                 0x084
+#define QSERDES_V8_COM_DEC_START_MODE0                 0x088
+#define QSERDES_V8_COM_DEC_START_MSB_MODE0             0x08c
+#define QSERDES_V8_COM_DIV_FRAC_START1_MODE0           0x090
+#define QSERDES_V8_COM_DIV_FRAC_START2_MODE0           0x094
+#define QSERDES_V8_COM_DIV_FRAC_START3_MODE0           0x098
+#define QSERDES_V8_COM_VCO_TUNE1_MODE0                 0x0a8
+#define QSERDES_V8_COM_VCO_TUNE2_MODE0                 0x0ac
+#define QSERDES_V8_COM_BG_TIMER                                0x0bc
+#define QSERDES_V8_COM_SSC_EN_CENTER                   0x0c0
+#define QSERDES_V8_COM_SSC_PER1                                0x0cc
+#define QSERDES_V8_COM_SSC_PER2                                0x0d0
+#define QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN             0x0dc
+#define QSERDES_V8_COM_SYSCLK_BUF_ENABLE               0x0e8
+#define QSERDES_V8_COM_SYSCLK_EN_SEL                   0x110
+#define QSERDES_V8_COM_RESETSM_CNTRL                   0x118
+#define QSERDES_V8_COM_LOCK_CMP_CFG                    0x124
+#define QSERDES_V8_COM_VCO_TUNE_MAP                    0x140
+#define QSERDES_V8_COM_CORE_CLK_EN                     0x170
+#define QSERDES_V8_COM_CMN_CONFIG_1                    0x174
+#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1            0x1a4
+#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2            0x1a8
+#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3            0x1ac
+#define QSERDES_V8_COM_ADDITIONAL_MISC                 0x1b4
+#define QSERDES_V8_COM_CMN_STATUS                      0x2c8
+#define QSERDES_V8_COM_C_READY_STATUS                  0x2f0
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v8.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v8.h
new file mode 100644 (file)
index 0000000..4cb8b17
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v8.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V8_H_
+#define QCOM_PHY_QMP_QSERDES_TXRX_V8_H_
+
+#define QSERDES_V8_TX_TX_EMP_POST1_LVL                 0x00c
+#define QSERDES_V8_TX_TX_DRV_LVL                       0x014
+#define QSERDES_V8_TX_RES_CODE_LANE_TX                 0x034
+#define QSERDES_V8_TX_RES_CODE_LANE_RX                 0x038
+#define QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX          0x03c
+#define QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX          0x040
+#define QSERDES_V8_TX_TRANSCEIVER_BIAS_EN              0x054
+#define QSERDES_V8_TX_HIGHZ_DRVR_EN                    0x058
+#define QSERDES_V8_TX_TX_POL_INV                       0x05c
+#define QSERDES_V8_TX_LANE_MODE_1                      0x084
+#define QSERDES_V8_TX_LANE_MODE_2                      0x088
+#define QSERDES_V8_TX_LANE_MODE_3                      0x08c
+#define QSERDES_V8_TX_LANE_MODE_4                      0x090
+#define QSERDES_V8_TX_LANE_MODE_5                      0x094
+#define QSERDES_V8_TX_RCV_DETECT_LVL_2                 0x0a4
+#define QSERDES_V8_TX_PI_QEC_CTRL                      0x0e4
+
+#define QSERDES_V8_RX_UCDR_FO_GAIN                     0x008
+#define QSERDES_V8_RX_UCDR_SO_GAIN                     0x014
+#define QSERDES_V8_RX_UCDR_SVS_FO_GAIN                 0x020
+#define QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN            0x030
+#define QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE    0x034
+#define QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW          0x03c
+#define QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH         0x040
+#define QSERDES_V8_RX_UCDR_PI_CONTROLS                 0x044
+#define QSERDES_V8_RX_UCDR_SB2_THRESH1                 0x04c
+#define QSERDES_V8_RX_UCDR_SB2_THRESH2                 0x050
+#define QSERDES_V8_RX_UCDR_SB2_GAIN1                   0x054
+#define QSERDES_V8_RX_UCDR_SB2_GAIN2                   0x058
+#define QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE           0x060
+#define QSERDES_V8_RX_VGA_CAL_CNTRL1                   0x0d4
+#define QSERDES_V8_RX_VGA_CAL_CNTRL2                   0x0d8
+#define QSERDES_V8_RX_GM_CAL                           0x0dc
+#define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2            0x0ec
+#define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3            0x0f0
+#define QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4            0x0f4
+#define QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW              0x0f8
+#define QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH             0x0fc
+#define QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1      0x110
+#define QSERDES_V8_RX_SIGDET_ENABLES                   0x118
+#define QSERDES_V8_RX_SIGDET_CNTRL                     0x11c
+#define QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL            0x124
+#define QSERDES_V8_RX_RX_MODE_00_LOW                   0x15c
+#define QSERDES_V8_RX_RX_MODE_00_HIGH                  0x160
+#define QSERDES_V8_RX_RX_MODE_00_HIGH2                 0x164
+#define QSERDES_V8_RX_RX_MODE_00_HIGH3                 0x168
+#define QSERDES_V8_RX_RX_MODE_00_HIGH4                 0x16c
+#define QSERDES_V8_RX_RX_MODE_01_LOW                   0x170
+#define QSERDES_V8_RX_RX_MODE_01_HIGH                  0x174
+#define QSERDES_V8_RX_RX_MODE_01_HIGH2                 0x178
+#define QSERDES_V8_RX_RX_MODE_01_HIGH3                 0x17c
+#define QSERDES_V8_RX_RX_MODE_01_HIGH4                 0x180
+#define QSERDES_V8_RX_DFE_EN_TIMER                     0x1a0
+#define QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET         0x1a4
+#define QSERDES_V8_RX_DCC_CTRL1                                0x1a8
+#define QSERDES_V8_RX_VTH_CODE                         0x1b0
+#define QSERDES_V8_RX_SIGDET_CAL_CTRL1                 0x1e4
+#define QSERDES_V8_RX_SIGDET_CAL_TRIM                  0x1f8
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index d0f41e4aaa855fc3ee088afc833b214277b7e2b0..8148853ff275b0526cb47a158d332af1d74e0abf 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -30,6 +30,9 @@
 #include "phy-qcom-qmp-qserdes-com-v7.h"
 #include "phy-qcom-qmp-qserdes-txrx-v7.h"
 
+#include "phy-qcom-qmp-qserdes-com-v8.h"
+#include "phy-qcom-qmp-qserdes-txrx-v8.h"
+
 #include "phy-qcom-qmp-qserdes-pll.h"
 
 #include "phy-qcom-qmp-pcs-v2.h"
@@ -52,6 +55,8 @@
 
 #include "phy-qcom-qmp-pcs-v7.h"
 
+#include "phy-qcom-qmp-pcs-v8.h"
+
 /* QPHY_SW_RESET bit */
 #define SW_RESET                               BIT(0)
 /* QPHY_POWER_DOWN_CONTROL */