Accept DMB (mcr 15, 0, rT, c7, c10, 5) for any rT <= 14,

not just when rT = r0.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2257

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index 1adcf0725eb0ee03374a0d41aa81afc2ebdf969f..c51de011ce04e6b7a77b3faa8e36db40b013664b 100644 (file)
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -14051,6 +14051,19 @@ DisResult disInstr_ARM_WRK (
       means we don't know which they are, so the back end has to
       re-emit them all when it comes acrosss an IR Fence.
    */
+   /* v6 */ /* mcr 15, 0, rT, c7, c10, 5 */
+   if (0xEE070FBA == (insn & 0xFFFF0FFF)) {
+      UInt rT = INSN(15,12);
+      if (rT <= 14) {
+         /* mcr 15, 0, rT, c7, c10, 5 (v6) equiv to DMB (v7).  Data
+            Memory Barrier -- ensures ordering of memory accesses. */
+         stmt( IRStmt_MBE(Imbe_Fence) );
+         DIP("mcr 15, 0, r%u, c7, c10, 5 (data memory barrier)\n", rT);
+         goto decode_success;
+      }
+      /* fall through */
+   }
+   /* other flavours of barrier */
    switch (insn) {
       case 0xEE070F9A: /* v6 */
          /* mcr 15, 0, r0, c7, c10, 4 (v6) equiv to DSB (v7).  Data
@@ -14058,12 +14071,6 @@ DisResult disInstr_ARM_WRK (
          stmt( IRStmt_MBE(Imbe_Fence) );
          DIP("mcr 15, 0, r0, c7, c10, 4 (data synch barrier)\n");
          goto decode_success;
-      case 0xEE070FBA: /* v6 */
-         /* mcr 15, 0, r0, c7, c10, 5 (v6) equiv to DMB (v7).  Data
-            Memory Barrier -- ensures ordering of memory accesses. */
-         stmt( IRStmt_MBE(Imbe_Fence) );
-         DIP("mcr 15, 0, r0, c7, c10, 5 (data memory barrier)\n");
-         goto decode_success;
       case 0xEE070F95: /* v6 */
          /* mcr 15, 0, r0, c7, c5, 4 (v6) equiv to ISB (v7).
             Instruction Synchronisation Barrier (or Flush Prefetch