ASoC: fsl_xcvr: Add Counter registers

[ Upstream commit 107d170dc46e14cfa575d1b995107ef2f2e51dfe ]

These counter registers are part of register list,
add them to complete the register map

- DMAC counter control registers
- Data path Timestamp counter register
- Data path bit counter register
- Data path bit count timestamp register
- Data path bit read timestamp register

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1666940627-7611-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Stable-dep-of: 73b97d46dde6 ("ASoC: fsl_xcvr: clear the channel status control memory")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c
index d0556c79fdb1531aaa6f84d53c2e6fcc3da82c24..1feb5758245f0af20ab7fb3445b781ca1fcf1366 100644 (file)
--- a/sound/soc/fsl/fsl_xcvr.c
+++ b/sound/soc/fsl/fsl_xcvr.c
@@ -933,6 +933,14 @@ static const struct reg_default fsl_xcvr_reg_defaults[] = {
        { FSL_XCVR_RX_DPTH_CTRL_SET,    0x00002C89 },
        { FSL_XCVR_RX_DPTH_CTRL_CLR,    0x00002C89 },
        { FSL_XCVR_RX_DPTH_CTRL_TOG,    0x00002C89 },
+       { FSL_XCVR_RX_DPTH_CNTR_CTRL,   0x00000000 },
+       { FSL_XCVR_RX_DPTH_CNTR_CTRL_SET, 0x00000000 },
+       { FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
+       { FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
+       { FSL_XCVR_RX_DPTH_TSCR, 0x00000000 },
+       { FSL_XCVR_RX_DPTH_BCR,  0x00000000 },
+       { FSL_XCVR_RX_DPTH_BCTR, 0x00000000 },
+       { FSL_XCVR_RX_DPTH_BCRR, 0x00000000 },
        { FSL_XCVR_TX_DPTH_CTRL,        0x00000000 },
        { FSL_XCVR_TX_DPTH_CTRL_SET,    0x00000000 },
        { FSL_XCVR_TX_DPTH_CTRL_CLR,    0x00000000 },
@@ -943,6 +951,14 @@ static const struct reg_default fsl_xcvr_reg_defaults[] = {
        { FSL_XCVR_TX_CS_DATA_3,        0x00000000 },
        { FSL_XCVR_TX_CS_DATA_4,        0x00000000 },
        { FSL_XCVR_TX_CS_DATA_5,        0x00000000 },
+       { FSL_XCVR_TX_DPTH_CNTR_CTRL,   0x00000000 },
+       { FSL_XCVR_TX_DPTH_CNTR_CTRL_SET, 0x00000000 },
+       { FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR, 0x00000000 },
+       { FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG, 0x00000000 },
+       { FSL_XCVR_TX_DPTH_TSCR, 0x00000000 },
+       { FSL_XCVR_TX_DPTH_BCR,  0x00000000 },
+       { FSL_XCVR_TX_DPTH_BCTR, 0x00000000 },
+       { FSL_XCVR_TX_DPTH_BCRR, 0x00000000 },
        { FSL_XCVR_DEBUG_REG_0,         0x00000000 },
        { FSL_XCVR_DEBUG_REG_1,         0x00000000 },
 };
@@ -974,6 +990,14 @@ static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
        case FSL_XCVR_RX_DPTH_CTRL_SET:
        case FSL_XCVR_RX_DPTH_CTRL_CLR:
        case FSL_XCVR_RX_DPTH_CTRL_TOG:
+       case FSL_XCVR_RX_DPTH_CNTR_CTRL:
+       case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
+       case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
+       case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
+       case FSL_XCVR_RX_DPTH_TSCR:
+       case FSL_XCVR_RX_DPTH_BCR:
+       case FSL_XCVR_RX_DPTH_BCTR:
+       case FSL_XCVR_RX_DPTH_BCRR:
        case FSL_XCVR_TX_DPTH_CTRL:
        case FSL_XCVR_TX_DPTH_CTRL_SET:
        case FSL_XCVR_TX_DPTH_CTRL_CLR:
@@ -984,6 +1008,14 @@ static bool fsl_xcvr_readable_reg(struct device *dev, unsigned int reg)
        case FSL_XCVR_TX_CS_DATA_3:
        case FSL_XCVR_TX_CS_DATA_4:
        case FSL_XCVR_TX_CS_DATA_5:
+       case FSL_XCVR_TX_DPTH_CNTR_CTRL:
+       case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
+       case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
+       case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
+       case FSL_XCVR_TX_DPTH_TSCR:
+       case FSL_XCVR_TX_DPTH_BCR:
+       case FSL_XCVR_TX_DPTH_BCTR:
+       case FSL_XCVR_TX_DPTH_BCRR:
        case FSL_XCVR_DEBUG_REG_0:
        case FSL_XCVR_DEBUG_REG_1:
                return true;
@@ -1016,6 +1048,10 @@ static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg)
        case FSL_XCVR_RX_DPTH_CTRL_SET:
        case FSL_XCVR_RX_DPTH_CTRL_CLR:
        case FSL_XCVR_RX_DPTH_CTRL_TOG:
+       case FSL_XCVR_RX_DPTH_CNTR_CTRL:
+       case FSL_XCVR_RX_DPTH_CNTR_CTRL_SET:
+       case FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR:
+       case FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG:
        case FSL_XCVR_TX_DPTH_CTRL_SET:
        case FSL_XCVR_TX_DPTH_CTRL_CLR:
        case FSL_XCVR_TX_DPTH_CTRL_TOG:
@@ -1025,6 +1061,10 @@ static bool fsl_xcvr_writeable_reg(struct device *dev, unsigned int reg)
        case FSL_XCVR_TX_CS_DATA_3:
        case FSL_XCVR_TX_CS_DATA_4:
        case FSL_XCVR_TX_CS_DATA_5:
+       case FSL_XCVR_TX_DPTH_CNTR_CTRL:
+       case FSL_XCVR_TX_DPTH_CNTR_CTRL_SET:
+       case FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR:
+       case FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG:
                return true;
        default:
                return false;

diff --git a/sound/soc/fsl/fsl_xcvr.h b/sound/soc/fsl/fsl_xcvr.h
index 7f2853c60085e78cfe1b7aceac45a38df6ea344f..4769b0fca21def13c45e9e7d35e007e0c4fbf316 100644 (file)
--- a/sound/soc/fsl/fsl_xcvr.h
+++ b/sound/soc/fsl/fsl_xcvr.h
@@ -49,6 +49,16 @@
 #define FSL_XCVR_RX_DPTH_CTRL_CLR      0x188
 #define FSL_XCVR_RX_DPTH_CTRL_TOG      0x18c
 
+#define FSL_XCVR_RX_DPTH_CNTR_CTRL     0x1C0
+#define FSL_XCVR_RX_DPTH_CNTR_CTRL_SET 0x1C4
+#define FSL_XCVR_RX_DPTH_CNTR_CTRL_CLR 0x1C8
+#define FSL_XCVR_RX_DPTH_CNTR_CTRL_TOG 0x1CC
+
+#define FSL_XCVR_RX_DPTH_TSCR          0x1D0
+#define FSL_XCVR_RX_DPTH_BCR           0x1D4
+#define FSL_XCVR_RX_DPTH_BCTR          0x1D8
+#define FSL_XCVR_RX_DPTH_BCRR          0x1DC
+
 #define FSL_XCVR_TX_DPTH_CTRL          0x220 /* TX datapath ctrl reg */
 #define FSL_XCVR_TX_DPTH_CTRL_SET      0x224
 #define FSL_XCVR_TX_DPTH_CTRL_CLR      0x228
@@ -59,6 +69,17 @@
 #define FSL_XCVR_TX_CS_DATA_3          0x23C
 #define FSL_XCVR_TX_CS_DATA_4          0x240
 #define FSL_XCVR_TX_CS_DATA_5          0x244
+
+#define FSL_XCVR_TX_DPTH_CNTR_CTRL     0x260
+#define FSL_XCVR_TX_DPTH_CNTR_CTRL_SET 0x264
+#define FSL_XCVR_TX_DPTH_CNTR_CTRL_CLR 0x268
+#define FSL_XCVR_TX_DPTH_CNTR_CTRL_TOG 0x26C
+
+#define FSL_XCVR_TX_DPTH_TSCR          0x270
+#define FSL_XCVR_TX_DPTH_BCR           0x274
+#define FSL_XCVR_TX_DPTH_BCTR          0x278
+#define FSL_XCVR_TX_DPTH_BCRR          0x27C
+
 #define FSL_XCVR_DEBUG_REG_0           0x2E0
 #define FSL_XCVR_DEBUG_REG_1           0x2F0