spi: cadence-quadspi: Flush posted register writes before INDAC access

commit 29e0b471ccbd674d20d4bbddea1a51e7105212c5 upstream.

cqspi_indirect_read_execute() and cqspi_indirect_write_execute() first
set the enable bit on APB region and then start reading/writing to the
AHB region. On TI K3 SoCs these regions lie on different endpoints. This
means that the order of the two operations is not guaranteed, and they
might be reordered at the interconnect level.

It is possible for the AHB write to be executed before the APB write to
enable the indirect controller, causing the transaction to be invalid
and the write erroring out. Read back the APB region write before
accessing the AHB region to make sure the write got flushed and the race
condition is eliminated.

Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller")
CC: stable@vger.kernel.org
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
Signed-off-by: Pratyush Yadav <pratyush@kernel.org>
Signed-off-by: Santhosh Kumar K <s-k6@ti.com>
Message-ID: <20250905185958.3575037-2-s-k6@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index d288e9d9c18739186bebe48ee81b76d525c51b5b..29ae6ee295345ebbdb007dd24229354ff8543384 100644 (file)
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -765,6 +765,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata,
        reinit_completion(&cqspi->transfer_complete);
        writel(CQSPI_REG_INDIRECTRD_START_MASK,
               reg_base + CQSPI_REG_INDIRECTRD);
+       readl(reg_base + CQSPI_REG_INDIRECTRD); /* Flush posted write. */
 
        while (remaining > 0) {
                if (use_irq &&
@@ -1091,6 +1092,8 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata,
        reinit_completion(&cqspi->transfer_complete);
        writel(CQSPI_REG_INDIRECTWR_START_MASK,
               reg_base + CQSPI_REG_INDIRECTWR);
+       readl(reg_base + CQSPI_REG_INDIRECTWR); /* Flush posted write. */
+
        /*
         * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access
         * Controller programming sequence, couple of cycles of