re PR target/39327 (Incorrect addsub/unpck patterns in sse.md)

2009-02-28  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/39327
	* config/i386/sse.md (avx_addsubv8sf3): Correct item bits.
	(avx_addsubv4df3): Likewise.
	(*avx_addsubv4sf3): Likewise.
	(sse3_addsubv4sf3): Likewise.
	(*avx_addsubv2df3): Likewise.
	(sse3_addsubv2df3): Likewise.
	(avx_unpckhps256): Correct item selectors.
	(avx_unpcklps256): Likewise.
	(avx_unpckhpd256): Likewise.
	(avx_unpcklpd256): Likewise.

From-SVN: r144498

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 87578499cf096fa2a443ff5f069edca149982c56..4bf1384d6da14692801f1894a09a2170d84caa32 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2009-02-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/39327
+       * config/i386/sse.md (avx_addsubv8sf3): Correct item bits.
+       (avx_addsubv4df3): Likewise.
+       (*avx_addsubv4sf3): Likewise.
+       (sse3_addsubv4sf3): Likewise.
+       (*avx_addsubv2df3): Likewise.
+       (sse3_addsubv2df3): Likewise.
+       (avx_unpckhps256): Correct item selectors.
+       (avx_unpcklps256): Likewise.
+       (avx_unpckhpd256): Likewise.
+       (avx_unpcklpd256): Likewise.
+
 2009-02-28  Jan Hubicka  <jh@suse.cz>
 
        * tree-inline.c (expand_call_inline): Avoid duplicate declarations of

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index a54133378b592cbfda4a82278fe51872c0b1a4f8..db5b64fc3a817148a4cc29f5d0c9bf548b3bacc8 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1101,7 +1101,7 @@
            (match_operand:V8SF 1 "register_operand" "x")
            (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
          (minus:V8SF (match_dup 1) (match_dup 2))
-         (const_int 85)))]
+         (const_int 66)))]
   "TARGET_AVX"
   "vaddsubps\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseadd")
@@ -1115,7 +1115,7 @@
            (match_operand:V4DF 1 "register_operand" "x")
            (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
          (minus:V4DF (match_dup 1) (match_dup 2))
-         (const_int 5)))]
+         (const_int 6)))]
   "TARGET_AVX"
   "vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseadd")
@@ -1129,7 +1129,7 @@
            (match_operand:V4SF 1 "register_operand" "x")
            (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
          (minus:V4SF (match_dup 1) (match_dup 2))
-         (const_int 5)))]
+         (const_int 6)))]
   "TARGET_AVX"
   "vaddsubps\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseadd")
@@ -1143,7 +1143,7 @@
            (match_operand:V4SF 1 "register_operand" "0")
            (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
          (minus:V4SF (match_dup 1) (match_dup 2))
-         (const_int 5)))]
+         (const_int 6)))]
   "TARGET_SSE3"
   "addsubps\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseadd")
@@ -1157,7 +1157,7 @@
            (match_operand:V2DF 1 "register_operand" "x")
            (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
          (minus:V2DF (match_dup 1) (match_dup 2))
-         (const_int 1)))]
+         (const_int 2)))]
   "TARGET_AVX"
   "vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseadd")
@@ -1171,7 +1171,7 @@
            (match_operand:V2DF 1 "register_operand" "0")
            (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
          (minus:V2DF (match_dup 1) (match_dup 2))
-         (const_int 1)))]
+         (const_int 2)))]
   "TARGET_SSE3"
   "addsubpd\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseadd")
@@ -3059,10 +3059,10 @@
          (vec_concat:V16SF
            (match_operand:V8SF 1 "register_operand" "x")
            (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
-         (parallel [(const_int 2) (const_int 6)
-                    (const_int 3) (const_int 7)
-                    (const_int 10) (const_int 14)
-                    (const_int 11) (const_int 15)])))]
+         (parallel [(const_int 2) (const_int 10)
+                    (const_int 3) (const_int 11)
+                    (const_int 6) (const_int 14)
+                    (const_int 7) (const_int 15)])))]
   "TARGET_AVX"
   "vunpckhps\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog")
@@ -3102,10 +3102,10 @@
          (vec_concat:V16SF
            (match_operand:V8SF 1 "register_operand" "x")
            (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
-         (parallel [(const_int 0) (const_int 4)
-                    (const_int 1) (const_int 5)
-                    (const_int 8) (const_int 12)
-                    (const_int 9) (const_int 13)])))]
+         (parallel [(const_int 0) (const_int 8)
+                    (const_int 1) (const_int 9)
+                    (const_int 4) (const_int 12)
+                    (const_int 5) (const_int 13)])))]
   "TARGET_AVX"
   "vunpcklps\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog")
@@ -3902,7 +3902,7 @@
          (vec_concat:V8DF
            (match_operand:V4DF 1 "register_operand" "x")
            (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
-         (parallel [(const_int 2) (const_int 6)
+         (parallel [(const_int 1) (const_int 5)
                     (const_int 3) (const_int 7)])))]
   "TARGET_AVX"
   "vunpckhpd\t{%2, %1, %0|%0, %1, %2}"
@@ -4023,7 +4023,7 @@
            (match_operand:V4DF 1 "register_operand" "x")
            (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
          (parallel [(const_int 0) (const_int 4)
-                    (const_int 1) (const_int 5)])))]
+                    (const_int 2) (const_int 6)])))]
   "TARGET_AVX"
   "vunpcklpd\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog")