]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
RDMA/mlx5: Fix UMR modifying of mkey page size
authorEdward Srouji <edwards@nvidia.com>
Wed, 9 Jul 2025 06:42:09 +0000 (09:42 +0300)
committerLeon Romanovsky <leon@kernel.org>
Sun, 13 Jul 2025 06:57:30 +0000 (02:57 -0400)
When changing the page size on an mkey, the driver needs to set the
appropriate bits in the mkey mask to indicate which fields are being
modified.
The 6th bit of a page size in mlx5 driver is considered an extension,
and this bit has a dedicated capability and mask bits.

Previously, the driver was not setting this mask in the mkey mask when
performing page size changes, regardless of its hardware support,
potentially leading to an incorrect page size updates.

This fixes the issue by setting the relevant bit in the mkey mask when
performing page size changes on an mkey and the 6th bit of this field is
supported by the hardware.

Fixes: cef7dde8836a ("net/mlx5: Expand mkey page size to support 6 bits")
Signed-off-by: Edward Srouji <edwards@nvidia.com>
Reviewed-by: Michael Guralnik <michaelgur@nvidia.com>
Link: https://patch.msgid.link/9f43a9c73bf2db6085a99dc836f7137e76579f09.1751979184.git.leon@kernel.org
Signed-off-by: Leon Romanovsky <leon@kernel.org>
drivers/infiniband/hw/mlx5/umr.c
include/linux/mlx5/device.h

index 5be4426a28844992334ab6d4ff6e52f04f177ef2..25601dea9e30101df0fea04bb5f04cdd1a01484d 100644 (file)
@@ -32,13 +32,15 @@ static __be64 get_umr_disable_mr_mask(void)
        return cpu_to_be64(result);
 }
 
-static __be64 get_umr_update_translation_mask(void)
+static __be64 get_umr_update_translation_mask(struct mlx5_ib_dev *dev)
 {
        u64 result;
 
        result = MLX5_MKEY_MASK_LEN |
                 MLX5_MKEY_MASK_PAGE_SIZE |
                 MLX5_MKEY_MASK_START_ADDR;
+       if (MLX5_CAP_GEN_2(dev->mdev, umr_log_entity_size_5))
+               result |= MLX5_MKEY_MASK_PAGE_SIZE_5;
 
        return cpu_to_be64(result);
 }
@@ -654,7 +656,7 @@ static void mlx5r_umr_final_update_xlt(struct mlx5_ib_dev *dev,
                flags & MLX5_IB_UPD_XLT_ENABLE || flags & MLX5_IB_UPD_XLT_ADDR;
 
        if (update_translation) {
-               wqe->ctrl_seg.mkey_mask |= get_umr_update_translation_mask();
+               wqe->ctrl_seg.mkey_mask |= get_umr_update_translation_mask(dev);
                if (!mr->ibmr.length)
                        MLX5_SET(mkc, &wqe->mkey_seg, length64, 1);
        }
index 6822cfa5f4ad31ef6fb61be2dcfae3ac9a46d659..9d2467f982ad4697f0b36f6975b820c3a41fc78a 100644 (file)
@@ -280,6 +280,7 @@ enum {
        MLX5_MKEY_MASK_SMALL_FENCE      = 1ull << 23,
        MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE   = 1ull << 25,
        MLX5_MKEY_MASK_FREE                     = 1ull << 29,
+       MLX5_MKEY_MASK_PAGE_SIZE_5              = 1ull << 42,
        MLX5_MKEY_MASK_RELAXED_ORDERING_READ    = 1ull << 47,
 };