drm/amd/display: Initialize a default to phyd32clk

[WHAT]
phyd32clk may not be assigned before used. Give it a value based
on the default from get_phyd32clk_src().

This is reported as an UNINIT error by Coverity.

Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 22c1d5e684207cee53be80ada9eaecb63131f497..86400938abd2ea0a64da616694b5a79a4cc3fa7e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -948,7 +948,7 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx)
        const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
        struct dc *dc = pipe_ctx->stream->ctx->dc;
        struct dccg *dccg = dc->res_pool->dccg;
-       enum phyd32clk_clock_source phyd32clk;
+       enum phyd32clk_clock_source phyd32clk = PHYD32CLKA;
        int dp_hpo_inst = 0;
        unsigned int tmds_div = PIXEL_RATE_DIV_NA;
        unsigned int unused_div = PIXEL_RATE_DIV_NA;