drm/msm/a6xx: Replace '2' with BIT(1) in level2_swizzling_dis calc

ubwc_swizzle is a bitmask. Check for a bit to make it more obvious.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660973/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index f998dc240d4997aad8ffdef629cf9a19275b6e27..07212e3b9eac4d79289c8c370de6f165a341d1b8 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -687,12 +687,12 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
         */
        BUG_ON(adreno_gpu->ubwc_config.highest_bank_bit < 13);
        u32 hbb = adreno_gpu->ubwc_config.highest_bank_bit - 13;
+       u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1));
        bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg);
        bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
        u8 uavflagprd_inv = 0;
        u32 hbb_hi = hbb >> 2;
        u32 hbb_lo = hbb & 3;
-       u32 level2_swizzling_dis = !(adreno_gpu->ubwc_config.ubwc_swizzle & 2);
 
        if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu))
                uavflagprd_inv = 2;