clk: renesas: r8a779g0: Add FCPVX clocks

Add the FCPVX modules clock for Renesas R-Car V4H (R8A779G0) SoC.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com>
Link: https://lore.kernel.org/20241220-rcar-v4h-vspx-v4-1-7dc1812585ad@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 55c8dd032fc325c63727f21dc4d38b8e08ce0ca0..f41e7382a5e66ed15ce4e977691c8b4bdf18d255 100644 (file)
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -238,6 +238,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
        DEF_MOD("pfc2",         917,    R8A779G0_CLK_CP),
        DEF_MOD("pfc3",         918,    R8A779G0_CLK_CP),
        DEF_MOD("tsc",          919,    R8A779G0_CLK_CL16M),
+       DEF_MOD("fcpvx0",       1100,   R8A779G0_CLK_S0D1_VIO),
+       DEF_MOD("fcpvx1",       1101,   R8A779G0_CLK_S0D1_VIO),
        DEF_MOD("tsn",          2723,   R8A779G0_CLK_S0D4_HSC),
        DEF_MOD("ssiu",         2926,   R8A779G0_CLK_S0D6_PER),
        DEF_MOD("ssi",          2927,   R8A779G0_CLK_S0D6_PER),