]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: qcom: lemans: Correct QUP interrupt numbers
authorViken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Wed, 25 Mar 2026 13:00:37 +0000 (18:30 +0530)
committerBjorn Andersson <andersson@kernel.org>
Thu, 26 Mar 2026 14:40:56 +0000 (09:40 -0500)
Fix GIC_SPI interrupt numbers for QUPv3 SE6 nodes on Lemans SoC.
Using incorrect interrupt lines can prevent IRQs from triggering
and break I2C, SPI, and UART operation.

Fixes: 34a407316b7d3 ("arm64: dts: qcom: sa8775p: Populate additional UART DT nodes")
Fixes: 1b2d7ad5ac14d ("arm64: dts: qcom: sa8775p: add missing spi nodes")
Fixes: ee2f5f906d69d ("arm64: dts: qcom: sa8775p: add missing i2c nodes")
Cc: stable@vger.kernel.org
Signed-off-by: Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260325-lemans-irq-num-v1-1-a470d544966a@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arch/arm64/boot/dts/qcom/lemans.dtsi

index f565067bda3187938576296ebd673d6c9c1ff7a0..05c0888e2bc697c0be4b143a2e1694a4d494b924 100644 (file)
                                reg = <0x0 0x898000 0x0 0x4000>;
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
                                clock-names = "se";
                                pinctrl-0 = <&qup_i2c20_default>;
                                reg = <0x0 0x898000 0x0 0x4000>;
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
                                clock-names = "se";
                                pinctrl-0 = <&qup_spi20_default>;
                        uart20: serial@898000 {
                                compatible = "qcom,geni-uart";
                                reg = <0x0 0x00898000 0x0 0x4000>;
-                               interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
                                clock-names = "se";
                                pinctrl-0 = <&qup_uart20_default>;
                                reg = <0x0 0xa98000 0x0 0x4000>;
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
                                clock-names = "se";
                                pinctrl-0 = <&qup_i2c13_default>;