Handle NOP.W (Thumb) and NOP (ARM). Partial fix for #253636.

Add a comment re conditionalisation of Thumb memory barrier insns.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2064

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index 4e1d740d51ec09e788dc3dd1ce47a0b16381c63a..9a2e97c889ed67caa8313c8337ad6962b7e11945 100644 (file)
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -13808,6 +13808,12 @@ DisResult disInstr_ARM_WRK (
       }
    }
 
+   /* ------------------- NOP ------------------ */
+   if (0x0320F000 == (insn & 0x0FFFFFFF)) {
+      DIP("nop%s\n", nCC(INSN_COND));
+      goto decode_success;
+   }
+
    /* ----------------------------------------------------------- */
    /* -- ARMv7 instructions                                    -- */
    /* ----------------------------------------------------------- */
@@ -17643,6 +17649,10 @@ DisResult disInstr_THUMB_WRK (
 
    /* -------------- v7 barrier insns -------------- */
    if (INSN0(15,0) == 0xF3BF && (INSN1(15,0) & 0xFF0F) == 0x8F0F) {
+      /* XXX this isn't really right, is it?  The generated IR does
+         them unconditionally.  I guess it doesn't matter since it
+         doesn't do any harm to do them even when the guarding
+         condition is false -- it's just a performance loss. */
       switch (INSN1(7,4)) {
          case 0x4: /* DSB */
             stmt( IRStmt_MBE(Imbe_Fence) );
@@ -17661,6 +17671,12 @@ DisResult disInstr_THUMB_WRK (
       }
    }
 
+   /* ------------------- NOP ------------------ */
+   if (INSN0(15,0) == 0xF3AF && INSN1(15,0) == 0x8000) {
+      DIP("nop\n");
+      goto decode_success;
+   }
+
    /* ----------------------------------------------------------- */
    /* -- VFP (CP 10, CP 11) instructions (in Thumb mode)       -- */
    /* ----------------------------------------------------------- */