Find the default size required and use the helper funcction to set gart size.
Suggested-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
adev->gmc.visible_vram_size = adev->gmc.aper_size;
/* set the gart size */
- if (amdgpu_gart_size == -1) {
- switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
- default:
- adev->gmc.gart_size = 512ULL << 20;
- break;
- case IP_VERSION(10, 3, 1): /* DCE SG support */
- case IP_VERSION(10, 3, 3): /* DCE SG support */
- case IP_VERSION(10, 3, 6): /* DCE SG support */
- case IP_VERSION(10, 3, 7): /* DCE SG support */
- adev->gmc.gart_size = 1024ULL << 20;
- break;
- }
- } else {
- adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+ switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
+ case IP_VERSION(10, 3, 1): /* DCE SG support */
+ case IP_VERSION(10, 3, 3): /* DCE SG support */
+ case IP_VERSION(10, 3, 6): /* DCE SG support */
+ case IP_VERSION(10, 3, 7): /* DCE SG support */
+ amdgpu_gmc_set_gart_size(adev, SZ_1G);
+ break;
+ default:
+ amdgpu_gmc_set_gart_size(adev, SZ_512M);
+ break;
}
gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
/* set the gart size */
- if (amdgpu_gart_size == -1)
- adev->gmc.gart_size = 512ULL << 20;
- else
- adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+ amdgpu_gmc_set_gart_size(adev, SZ_512M);
gmc_v11_0_vram_gtt_location(adev, &adev->gmc);
adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
/* set the gart size */
- if (amdgpu_gart_size == -1) {
- adev->gmc.gart_size = 512ULL << 20;
- } else
- adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+ amdgpu_gmc_set_gart_size(adev, SZ_512M);
gmc_v12_0_vram_gtt_location(adev, &adev->gmc);
adev->gmc.visible_vram_size = adev->gmc.aper_size;
/* set the gart size */
- if (amdgpu_gart_size == -1) {
- switch (adev->asic_type) {
- case CHIP_HAINAN: /* no MM engines */
- default:
- adev->gmc.gart_size = 256ULL << 20;
- break;
- case CHIP_VERDE: /* UVD, VCE do not support GPUVM */
- case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */
- case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
- case CHIP_OLAND: /* UVD, VCE do not support GPUVM */
- adev->gmc.gart_size = 1024ULL << 20;
- break;
- }
- } else {
- adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+ switch (adev->asic_type) {
+ case CHIP_VERDE: /* UVD, VCE do not support GPUVM */
+ case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */
+ case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
+ case CHIP_OLAND: /* UVD, VCE do not support GPUVM */
+ amdgpu_gmc_set_gart_size(adev, SZ_1G);
+ break;
+ case CHIP_HAINAN: /* no MM engines */
+ default:
+ amdgpu_gmc_set_gart_size(adev, SZ_256M);
+ break;
}
-
- adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
gmc_v6_0_vram_gtt_location(adev, &adev->gmc);
return 0;
adev->gmc.visible_vram_size = adev->gmc.aper_size;
/* set the gart size */
- if (amdgpu_gart_size == -1) {
- switch (adev->asic_type) {
- case CHIP_TOPAZ: /* no MM engines */
- default:
- adev->gmc.gart_size = 256ULL << 20;
- break;
+ switch (adev->asic_type) {
#ifdef CONFIG_DRM_AMDGPU_CIK
- case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
- case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */
- case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */
- case CHIP_KABINI: /* UVD, VCE do not support GPUVM */
- case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
- adev->gmc.gart_size = 1024ULL << 20;
- break;
+ case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
+ case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */
+ case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */
+ case CHIP_KABINI: /* UVD, VCE do not support GPUVM */
+ case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
+ amdgpu_gmc_set_gart_size(adev, SZ_1G);
+ break;
#endif
- }
- } else {
- adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+ case CHIP_TOPAZ: /* no MM engines */
+ default:
+ amdgpu_gmc_set_gart_size(adev, SZ_256M);
+ break;
}
-
- adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
gmc_v7_0_vram_gtt_location(adev, &adev->gmc);
return 0;
adev->gmc.visible_vram_size = adev->gmc.aper_size;
/* set the gart size */
- if (amdgpu_gart_size == -1) {
- switch (adev->asic_type) {
- case CHIP_POLARIS10: /* all engines support GPUVM */
- case CHIP_POLARIS11: /* all engines support GPUVM */
- case CHIP_POLARIS12: /* all engines support GPUVM */
- case CHIP_VEGAM: /* all engines support GPUVM */
- default:
- adev->gmc.gart_size = 256ULL << 20;
- break;
- case CHIP_TONGA: /* UVD, VCE do not support GPUVM */
- case CHIP_FIJI: /* UVD, VCE do not support GPUVM */
- case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
- case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */
- adev->gmc.gart_size = 1024ULL << 20;
- break;
- }
- } else {
- adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+ switch (adev->asic_type) {
+ case CHIP_TONGA: /* UVD, VCE do not support GPUVM */
+ case CHIP_FIJI: /* UVD, VCE do not support GPUVM */
+ case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
+ case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */
+ amdgpu_gmc_set_gart_size(adev, SZ_1G);
+ break;
+ case CHIP_POLARIS10: /* all engines support GPUVM */
+ case CHIP_POLARIS11: /* all engines support GPUVM */
+ case CHIP_POLARIS12: /* all engines support GPUVM */
+ case CHIP_VEGAM: /* all engines support GPUVM */
+ default:
+ amdgpu_gmc_set_gart_size(adev, SZ_256M);
+ break;
}
-
- adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
return 0;
adev->gmc.visible_vram_size = adev->gmc.aper_size;
/* set the gart size */
- if (amdgpu_gart_size == -1) {
- switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
- case IP_VERSION(9, 0, 1): /* all engines support GPUVM */
- case IP_VERSION(9, 2, 1): /* all engines support GPUVM */
- case IP_VERSION(9, 4, 0):
- case IP_VERSION(9, 4, 1):
- case IP_VERSION(9, 4, 2):
- case IP_VERSION(9, 4, 3):
- case IP_VERSION(9, 4, 4):
- case IP_VERSION(9, 5, 0):
- default:
- adev->gmc.gart_size = 512ULL << 20;
- break;
- case IP_VERSION(9, 1, 0): /* DCE SG support */
- case IP_VERSION(9, 2, 2): /* DCE SG support */
- case IP_VERSION(9, 3, 0):
- adev->gmc.gart_size = 1024ULL << 20;
- break;
- }
- } else {
- adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+ switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
+ case IP_VERSION(9, 1, 0): /* DCE SG support */
+ case IP_VERSION(9, 2, 2): /* DCE SG support */
+ case IP_VERSION(9, 3, 0):
+ amdgpu_gmc_set_gart_size(adev, SZ_1G);
+ break;
+ case IP_VERSION(9, 0, 1): /* all engines support GPUVM */
+ case IP_VERSION(9, 2, 1): /* all engines support GPUVM */
+ case IP_VERSION(9, 4, 0):
+ case IP_VERSION(9, 4, 1):
+ case IP_VERSION(9, 4, 2):
+ case IP_VERSION(9, 4, 3):
+ case IP_VERSION(9, 4, 4):
+ case IP_VERSION(9, 5, 0):
+ default:
+ amdgpu_gmc_set_gart_size(adev, SZ_512M);
+ break;
}
- adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
-
gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
return 0;