]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amdgpu: Use helper to set gart size
authorLijo Lazar <lijo.lazar@amd.com>
Thu, 30 Apr 2026 05:42:04 +0000 (11:12 +0530)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 5 May 2026 13:56:51 +0000 (09:56 -0400)
Find the default size required and use the helper funcction to set gart size.

Suggested-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

index e1ace7d44ffdfd247b1c3ec2c979155ddd02653e..8523833a74fbf455bb6513be5921eb25699c840b 100644 (file)
@@ -707,20 +707,16 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
        adev->gmc.visible_vram_size = adev->gmc.aper_size;
 
        /* set the gart size */
-       if (amdgpu_gart_size == -1) {
-               switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
-               default:
-                       adev->gmc.gart_size = 512ULL << 20;
-                       break;
-               case IP_VERSION(10, 3, 1):   /* DCE SG support */
-               case IP_VERSION(10, 3, 3):   /* DCE SG support */
-               case IP_VERSION(10, 3, 6):   /* DCE SG support */
-               case IP_VERSION(10, 3, 7):   /* DCE SG support */
-                       adev->gmc.gart_size = 1024ULL << 20;
-                       break;
-               }
-       } else {
-               adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+       switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
+       case IP_VERSION(10, 3, 1):   /* DCE SG support */
+       case IP_VERSION(10, 3, 3):   /* DCE SG support */
+       case IP_VERSION(10, 3, 6):   /* DCE SG support */
+       case IP_VERSION(10, 3, 7):   /* DCE SG support */
+               amdgpu_gmc_set_gart_size(adev, SZ_1G);
+               break;
+       default:
+               amdgpu_gmc_set_gart_size(adev, SZ_512M);
+               break;
        }
 
        gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
index 94d6631ce0bce62be858625bcc8420475b9d3234..16388e3caea32131f284e3c464d2a77b40ab195d 100644 (file)
@@ -709,10 +709,7 @@ static int gmc_v11_0_mc_init(struct amdgpu_device *adev)
                adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 
        /* set the gart size */
-       if (amdgpu_gart_size == -1)
-               adev->gmc.gart_size = 512ULL << 20;
-       else
-               adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+       amdgpu_gmc_set_gart_size(adev, SZ_512M);
 
        gmc_v11_0_vram_gtt_location(adev, &adev->gmc);
 
index 5bdd4b9b789346cd8967f3ef415ef175fcb3ba68..586703ec0dfa0b4dd1500779f4fa2e26d1b6dfb3 100644 (file)
@@ -765,10 +765,7 @@ static int gmc_v12_0_mc_init(struct amdgpu_device *adev)
                adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
 
        /* set the gart size */
-       if (amdgpu_gart_size == -1) {
-               adev->gmc.gart_size = 512ULL << 20;
-       } else
-               adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+       amdgpu_gmc_set_gart_size(adev, SZ_512M);
 
        gmc_v12_0_vram_gtt_location(adev, &adev->gmc);
 
index cc272a96fcef010db0aef26318bf003b9724c655..af6944d2d330d1665bf0fe098a4e6a7f30efb972 100644 (file)
@@ -328,24 +328,18 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
        adev->gmc.visible_vram_size = adev->gmc.aper_size;
 
        /* set the gart size */
-       if (amdgpu_gart_size == -1) {
-               switch (adev->asic_type) {
-               case CHIP_HAINAN:    /* no MM engines */
-               default:
-                       adev->gmc.gart_size = 256ULL << 20;
-                       break;
-               case CHIP_VERDE:    /* UVD, VCE do not support GPUVM */
-               case CHIP_TAHITI:   /* UVD, VCE do not support GPUVM */
-               case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
-               case CHIP_OLAND:    /* UVD, VCE do not support GPUVM */
-                       adev->gmc.gart_size = 1024ULL << 20;
-                       break;
-               }
-       } else {
-               adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+       switch (adev->asic_type) {
+       case CHIP_VERDE:    /* UVD, VCE do not support GPUVM */
+       case CHIP_TAHITI:   /* UVD, VCE do not support GPUVM */
+       case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
+       case CHIP_OLAND:    /* UVD, VCE do not support GPUVM */
+               amdgpu_gmc_set_gart_size(adev, SZ_1G);
+               break;
+       case CHIP_HAINAN:    /* no MM engines */
+       default:
+               amdgpu_gmc_set_gart_size(adev, SZ_256M);
+               break;
        }
-
-       adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
        gmc_v6_0_vram_gtt_location(adev, &adev->gmc);
 
        return 0;
index bb16ba2ef6fd90deb2c6f7e5329a7cccf1460745..96023b4f5f923ead0715db5a075ce917d1376f6f 100644 (file)
@@ -394,27 +394,21 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
        adev->gmc.visible_vram_size = adev->gmc.aper_size;
 
        /* set the gart size */
-       if (amdgpu_gart_size == -1) {
-               switch (adev->asic_type) {
-               case CHIP_TOPAZ:     /* no MM engines */
-               default:
-                       adev->gmc.gart_size = 256ULL << 20;
-                       break;
+       switch (adev->asic_type) {
 #ifdef CONFIG_DRM_AMDGPU_CIK
-               case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
-               case CHIP_HAWAII:  /* UVD, VCE do not support GPUVM */
-               case CHIP_KAVERI:  /* UVD, VCE do not support GPUVM */
-               case CHIP_KABINI:  /* UVD, VCE do not support GPUVM */
-               case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
-                       adev->gmc.gart_size = 1024ULL << 20;
-                       break;
+       case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
+       case CHIP_HAWAII:  /* UVD, VCE do not support GPUVM */
+       case CHIP_KAVERI:  /* UVD, VCE do not support GPUVM */
+       case CHIP_KABINI:  /* UVD, VCE do not support GPUVM */
+       case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
+               amdgpu_gmc_set_gart_size(adev, SZ_1G);
+               break;
 #endif
-               }
-       } else {
-               adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+       case CHIP_TOPAZ:     /* no MM engines */
+       default:
+               amdgpu_gmc_set_gart_size(adev, SZ_256M);
+               break;
        }
-
-       adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
        gmc_v7_0_vram_gtt_location(adev, &adev->gmc);
 
        return 0;
index a59174f6bcc18bb1df632d282d608c044aab5235..b76fc4441eb7911cec16bcbbcc149fe4af1f8c30 100644 (file)
@@ -585,27 +585,21 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
        adev->gmc.visible_vram_size = adev->gmc.aper_size;
 
        /* set the gart size */
-       if (amdgpu_gart_size == -1) {
-               switch (adev->asic_type) {
-               case CHIP_POLARIS10: /* all engines support GPUVM */
-               case CHIP_POLARIS11: /* all engines support GPUVM */
-               case CHIP_POLARIS12: /* all engines support GPUVM */
-               case CHIP_VEGAM:     /* all engines support GPUVM */
-               default:
-                       adev->gmc.gart_size = 256ULL << 20;
-                       break;
-               case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
-               case CHIP_FIJI:    /* UVD, VCE do not support GPUVM */
-               case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
-               case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG support */
-                       adev->gmc.gart_size = 1024ULL << 20;
-                       break;
-               }
-       } else {
-               adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+       switch (adev->asic_type) {
+       case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
+       case CHIP_FIJI:    /* UVD, VCE do not support GPUVM */
+       case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
+       case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG support */
+               amdgpu_gmc_set_gart_size(adev, SZ_1G);
+               break;
+       case CHIP_POLARIS10: /* all engines support GPUVM */
+       case CHIP_POLARIS11: /* all engines support GPUVM */
+       case CHIP_POLARIS12: /* all engines support GPUVM */
+       case CHIP_VEGAM:     /* all engines support GPUVM */
+       default:
+               amdgpu_gmc_set_gart_size(adev, SZ_256M);
+               break;
        }
-
-       adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
        gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
 
        return 0;
index aca7841173f35469494d48e7d233bd6f7c9b8177..ced0f3941863f52963b49cc25e8f2e86e463dc38 100644 (file)
@@ -1731,31 +1731,25 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
        adev->gmc.visible_vram_size = adev->gmc.aper_size;
 
        /* set the gart size */
-       if (amdgpu_gart_size == -1) {
-               switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
-               case IP_VERSION(9, 0, 1):  /* all engines support GPUVM */
-               case IP_VERSION(9, 2, 1):  /* all engines support GPUVM */
-               case IP_VERSION(9, 4, 0):
-               case IP_VERSION(9, 4, 1):
-               case IP_VERSION(9, 4, 2):
-               case IP_VERSION(9, 4, 3):
-               case IP_VERSION(9, 4, 4):
-               case IP_VERSION(9, 5, 0):
-               default:
-                       adev->gmc.gart_size = 512ULL << 20;
-                       break;
-               case IP_VERSION(9, 1, 0):   /* DCE SG support */
-               case IP_VERSION(9, 2, 2):   /* DCE SG support */
-               case IP_VERSION(9, 3, 0):
-                       adev->gmc.gart_size = 1024ULL << 20;
-                       break;
-               }
-       } else {
-               adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
+       switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
+       case IP_VERSION(9, 1, 0):   /* DCE SG support */
+       case IP_VERSION(9, 2, 2):   /* DCE SG support */
+       case IP_VERSION(9, 3, 0):
+               amdgpu_gmc_set_gart_size(adev, SZ_1G);
+               break;
+       case IP_VERSION(9, 0, 1):  /* all engines support GPUVM */
+       case IP_VERSION(9, 2, 1):  /* all engines support GPUVM */
+       case IP_VERSION(9, 4, 0):
+       case IP_VERSION(9, 4, 1):
+       case IP_VERSION(9, 4, 2):
+       case IP_VERSION(9, 4, 3):
+       case IP_VERSION(9, 4, 4):
+       case IP_VERSION(9, 5, 0):
+       default:
+               amdgpu_gmc_set_gart_size(adev, SZ_512M);
+               break;
        }
 
-       adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
-
        gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
 
        return 0;