[1/4] aarch64: Convert UABDL and SABDL patterns to standard RTL codes

This is the first patch in a series to improve the RTL representation of the sum-of-absolute-differences patterns
in the backend. We can use standard RTL codes and remove some unspecs.
For UABDL and SABDL we have a widening of the result so we can represent uabdl (x, y) as (zero_extend (minus (smax (x, y) (smin (x, y)))))
and sabdl (x, y) as (zero_extend (minus (umax (x, y) (umin (x, y))))).
It is important to use zero_extend rather than sign_extend for the sabdl case, as the result of the absolute difference is still a positive unsigned value
(the signedness of the operation refers to the values being diffed, not the absolute value of the difference) that must be zero-extended.

Bootstrapped and tested on aarch64-none-linux-gnu (these intrinsics are reasonably well-covered by the advsimd-intrinsics.exp tests)

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (aarch64_<sur>abdl<mode>): Rename to...
	(aarch64_<su>abdl<mode>): ... This.  Use standard RTL ops instead of
	unspec.
	* config/aarch64/aarch64.md (UNSPEC_SABDL, UNSPEC_UABDL): Delete.
	* config/aarch64/iterators.md (ABDL): Delete.
	(sur): Remove handling of UNSPEC_SABDL and UNSPEC_UABDL.

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index d1e74a6704a04b16897809bcc69b3dd04119bf6c..b46eb1d3149def4dac24b86bf762f18f371323a9 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -899,14 +899,18 @@
   [(set_attr "type" "neon_abd<q>")]
 )
 
-
-(define_insn "aarch64_<sur>abdl<mode>"
+(define_insn "aarch64_<su>abdl<mode>"
   [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
-       (unspec:<VWIDE> [(match_operand:VD_BHSI 1 "register_operand" "w")
-                        (match_operand:VD_BHSI 2 "register_operand" "w")]
-       ABDL))]
+       (zero_extend:<VWIDE>
+         (minus:VD_BHSI
+           (USMAX:VD_BHSI
+             (match_operand:VD_BHSI 1 "register_operand" "w")
+             (match_operand:VD_BHSI 2 "register_operand" "w"))
+           (<max_opp>:VD_BHSI
+             (match_dup 1)
+             (match_dup 2)))))]
   "TARGET_SIMD"
-  "<sur>abdl\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
+  "<su>abdl\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
   [(set_attr "type" "neon_abd<q>")]
 )
 

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index eaa87bf02767263aab59faa4b511016ce7cd99ad..a1f35f26318902e1255b76d4dca3bc210ab8827b 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -206,7 +206,6 @@
     UNSPEC_RBIT
     UNSPEC_SABAL
     UNSPEC_SABAL2
-    UNSPEC_SABDL
     UNSPEC_SABDL2
     UNSPEC_SADALP
     UNSPEC_SCVTF
@@ -230,7 +229,6 @@
     UNSPEC_TLSLE48
     UNSPEC_UABAL
     UNSPEC_UABAL2
-    UNSPEC_UABDL
     UNSPEC_UABDL2
     UNSPEC_UADALP
     UNSPEC_UCVTF

diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index d0184c84a0b866c2216d1e3124f80cc464f85da9..b7d67a64ca12212ec133e4f1ec3001d750eb545a 100644 (file)
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -2570,9 +2570,6 @@
 ;; The unspec codes for the SABAL, UABAL AdvancedSIMD instructions.
 (define_int_iterator ABAL [UNSPEC_SABAL UNSPEC_UABAL])
 
-;; The unspec codes for the SABDL, UABDL AdvancedSIMD instructions.
-(define_int_iterator ABDL [UNSPEC_SABDL UNSPEC_UABDL])
-
 ;; The unspec codes for the SABAL2, UABAL2 AdvancedSIMD instructions.
 (define_int_iterator ABAL2 [UNSPEC_SABAL2 UNSPEC_UABAL2])
 
@@ -3362,7 +3359,6 @@
                      (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
                      (UNSPEC_SABAL "s") (UNSPEC_UABAL "u")
                      (UNSPEC_SABAL2 "s") (UNSPEC_UABAL2 "u")
-                     (UNSPEC_SABDL "s") (UNSPEC_UABDL "u")
                      (UNSPEC_SABDL2 "s") (UNSPEC_UABDL2 "u")
                      (UNSPEC_SADALP "s") (UNSPEC_UADALP "u")
                      (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")