drm/amd/powerplay: Set higher SCLK&MCLK frequency than dpm7 in OD (v2)

[ Upstream commit 5c16f36f6f003b4415237acca59384a074cd8030 ]

Fix the issue that SCLK&MCLK can't be set higher than dpm7 when
OD is enabled in SMU7.

v2: fix warning (Alex)

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Acked-by: Rex Zhu<rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 18b5b2ff47febeb13c0682994fb5e2bd57bb53ef..df2dce8b8e39d0d11f2117a971b26e13df049790 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3715,14 +3715,17 @@ static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr,
 static int smu7_generate_dpm_level_enable_mask(
                struct pp_hwmgr *hwmgr, const void *input)
 {
-       int result;
+       int result = 0;
        const struct phm_set_power_state_input *states =
                        (const struct phm_set_power_state_input *)input;
        struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
        const struct smu7_power_state *smu7_ps =
                        cast_const_phw_smu7_power_state(states->pnew_state);
 
-       result = smu7_trim_dpm_states(hwmgr, smu7_ps);
+       /*skip the trim if od is enabled*/
+       if (!hwmgr->od_enabled)
+               result = smu7_trim_dpm_states(hwmgr, smu7_ps);
+
        if (result)
                return result;