Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 803afadba546beaf35a26bc7cca0abe33bbcebf6..48cba6c3469b7ceaa0bc55a28590bec85d2e58f8 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,51 @@
+2024-06-04  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2021-04-29  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR rtl-optimization/100303
+       * rtl-ssa/accesses.cc (function_info::make_use_available): Take a
+       boolean that indicates whether the use will only be used in
+       debug instructions.  Treat it in the same way that existing
+       cross-EBB debug references would be handled if so.
+       (function_info::make_uses_available): Likewise.
+       * rtl-ssa/functions.h (function_info::make_uses_available): Update
+       prototype accordingly.
+       (function_info::make_uses_available): Likewise.
+       * fwprop.c (try_fwprop_subst): Update call accordingly.
+
+2024-06-04  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2023-02-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR rtl-optimization/108086
+       * rtl-ssa/insns.h (insn_info): Make m_num_defs a full unsigned int.
+       Adjust size-related commentary accordingly.
+
+2024-06-04  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2024-01-29  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR target/113281
+       * tree-vect-patterns.c (vect_recog_over_widening_pattern): Remove
+       workaround for right shifts.
+       (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
+       (vect_determine_precisions_from_range): Be more selective about
+       which codes can be narrowed based on their input and output ranges.
+       For shifts, require at least one more bit of precision than the
+       maximum shift amount.
+
+2024-06-04  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2024-05-24  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR tree-optimization/115192
+       * tree-data-ref.c (create_intersect_range_checks): Take the
+       alignment of the access sizes into account.
+
 2024-06-03  Uros Bizjak  <ubizjak@gmail.com>
 
        Backported from master:

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index f8e244336c65fbac77cfd782a6f2cd37e7853a15..3577d8c152d61ac9f72f780615a1e3e0952b6b94 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20240604
+20240605

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7b7f662990a65ba5bf9fc548f552b5483c934438..2ec97ae3d9aa2eaa1e9c7f2e25a94a4f6a04bbe8 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,31 @@
+2024-06-04  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2021-04-29  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR rtl-optimization/100303
+       * g++.dg/torture/pr100303.C: New file.
+
+2024-06-04  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2024-01-29  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR target/113281
+       * gcc.dg/vect/pr113281-1.c: New test.
+       * gcc.dg/vect/pr113281-2.c: Likewise.
+       * gcc.dg/vect/pr113281-3.c: Likewise.
+       * gcc.dg/vect/pr113281-4.c: Likewise.
+       * gcc.dg/vect/pr113281-5.c: Likewise.
+
+2024-06-04  Richard Sandiford  <richard.sandiford@arm.com>
+
+       Backported from master:
+       2024-05-24  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR tree-optimization/115192
+       * gcc.dg/vect/pr115192.c: New test.
+
 2024-06-03  Uros Bizjak  <ubizjak@gmail.com>
 
        Backported from master: