arm64: dts: qcom: sm8650: Add power-domain and iface clk for ice node

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for its own resources. Before accessing ICE hardware during probe, to
avoid potential unclocked register access issues (when clk_ignore_unused
is not passed on the kernel command line), in addition to the 'core' clock
the 'iface' clock should also be turned on by the driver. This can only be
done if the UFS_PHY_GDSC power domain is enabled. Specify both the
UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sm8650.

Fixes: 10e0246712951 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-10-5ccf5d7e2846@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 1604bc8cff3735abd36e60c26e1a995d80ed2714..e2d98cf6adca8fc0f08fa9fd53141538878b03d3 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -4081,7 +4081,11 @@
                                     "qcom,inline-crypto-engine";
                        reg = <0 0x01d88000 0 0x18000>;
 
-                       clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+                       clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+                                <&gcc GCC_UFS_PHY_AHB_CLK>;
+                       clock-names = "core",
+                                     "iface";
+                       power-domains = <&gcc UFS_PHY_GDSC>;
                };
 
                cryptobam: dma-controller@1dc4000 {