re PR target/19005 (Error: bad register name `%sil')

        PR target/19005
        * config/i386/i386.md (swaphi_1): Swap with swaphi_2, allow with
        optimize_size.
        (swapqi_1): Rename from swapqi.  Enable only for no partial reg
        stall and optimize_size.
        (swapqi_2): New.
        (swaphi_1, swaphi_2, swapqi_1): Add athlon_decode.
        (swapsi, swaphi_1, swaphi_2, swapqi_1, swapdi): Remove modrm override.

From-SVN: r92248

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5cc4be30cc90990153230c3f61a5b6c25ee6a1ca..be771aecadff849f14349644333710fe87756c3d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2004-12-15  Richard Henderson  <rth@redhat.com>
+
+        PR target/19005
+        * config/i386/i386.md (swaphi_1): Swap with swaphi_2, allow with
+        optimize_size.
+        (swapqi_1): Rename from swapqi.  Enable only for no partial reg
+        stall and optimize_size.
+        (swapqi_2): New.
+        (swaphi_1, swaphi_2, swapqi_1): Add athlon_decode.
+        (swapsi, swaphi_1, swaphi_2, swapqi_1, swapdi): Remove modrm override.
+
 2004-12-13  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 
        PR middle-end/18730

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index ceb0a5c8e9726479f80b72e3908e025c478ade2e..e5cb582cab40c275f974d91fe4108c68b16e5746 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1188,10 +1188,9 @@
   ""
   "xchg{l}\t%1, %0"
   [(set_attr "type" "imov")
+   (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
-   (set_attr "mode" "SI")
-   (set_attr "modrm" "0")
    (set_attr "ppro_uops" "few")])
 
 (define_expand "movhi"
@@ -1304,12 +1303,12 @@
        (match_operand:HI 1 "register_operand" "+r"))
    (set (match_dup 1)
        (match_dup 0))]
-  "TARGET_PARTIAL_REG_STALL"
-  "xchg{w}\t%1, %0"
+  "!TARGET_PARTIAL_REG_STALL || optimize_size"
+  "xchg{l}\t%k1, %k0"
   [(set_attr "type" "imov")
+   (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
-   (set_attr "mode" "HI")
-   (set_attr "modrm" "0")
+   (set_attr "athlon_decode" "vector")
    (set_attr "ppro_uops" "few")])
 
 (define_insn "*swaphi_2"
@@ -1317,12 +1316,12 @@
        (match_operand:HI 1 "register_operand" "+r"))
    (set (match_dup 1)
        (match_dup 0))]
-  "! TARGET_PARTIAL_REG_STALL"
-  "xchg{l}\t%k1, %k0"
+  "TARGET_PARTIAL_REG_STALL"
+  "xchg{w}\t%1, %0"
   [(set_attr "type" "imov")
+   (set_attr "mode" "HI")
    (set_attr "pent_pair" "np")
-   (set_attr "mode" "SI")
-   (set_attr "modrm" "0")
+   (set_attr "athlon_decode" "vector")
    (set_attr "ppro_uops" "few")])
 
 (define_expand "movstricthi"
@@ -1470,17 +1469,30 @@
   DONE;
 })
 
-(define_insn "*swapqi"
+(define_insn "*swapqi_1"
   [(set (match_operand:QI 0 "register_operand" "+r")
        (match_operand:QI 1 "register_operand" "+r"))
    (set (match_dup 1)
        (match_dup 0))]
-  ""
-  "xchg{b}\t%1, %0"
+  "!TARGET_PARTIAL_REG_STALL || optimize_size"
+  "xchg{l}\t%k1, %k0"
   [(set_attr "type" "imov")
+   (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
+   (set_attr "athlon_decode" "vector")
+   (set_attr "ppro_uops" "few")])
+
+(define_insn "*swapqi_2"
+  [(set (match_operand:QI 0 "register_operand" "+q")
+       (match_operand:QI 1 "register_operand" "+q"))
+   (set (match_dup 1)
+       (match_dup 0))]
+  "TARGET_PARTIAL_REG_STALL"
+  "xchg{b}\t%1, %0"
+  [(set_attr "type" "imov")
    (set_attr "mode" "QI")
-   (set_attr "modrm" "0")
+   (set_attr "pent_pair" "np")
+   (set_attr "athlon_decode" "vector")
    (set_attr "ppro_uops" "few")])
 
 (define_expand "movstrictqi"
@@ -1987,13 +1999,11 @@
   "TARGET_64BIT"
   "xchg{q}\t%1, %0"
   [(set_attr "type" "imov")
+   (set_attr "mode" "DI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
-   (set_attr "mode" "DI")
-   (set_attr "modrm" "0")
    (set_attr "ppro_uops" "few")])
 
-  
 (define_expand "movsf"
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
        (match_operand:SF 1 "general_operand" ""))]