clk: renesas: r9a09g047: Add RSCI clocks/resets

Add RSCI clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251027154615.115759-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 68f8b08bd16f3f603935b30829a3c5768f9e8be3..1e9896742a062e1891dc0434531c392c03ba8f62 100644 (file)
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -44,6 +44,9 @@ enum clk_ids {
        CLK_PLLCLN_DIV8,
        CLK_PLLCLN_DIV16,
        CLK_PLLCLN_DIV20,
+       CLK_PLLCLN_DIV64,
+       CLK_PLLCLN_DIV256,
+       CLK_PLLCLN_DIV1024,
        CLK_PLLDTY_ACPU,
        CLK_PLLDTY_ACPU_DIV2,
        CLK_PLLDTY_ACPU_DIV4,
@@ -142,6 +145,9 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
        DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
        DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
        DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),
+       DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64),
+       DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256),
+       DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024),
 
        DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
        DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
@@ -218,6 +224,106 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
                                                BUS_MSTOP(5, BIT(13))),
        DEF_MOD("wdt_3_clk_loco",               CLK_QEXTAL, 5, 2, 2, 18,
                                                BUS_MSTOP(5, BIT(13))),
+       DEF_MOD("rsci0_pclk",                   CLK_PLLCLN_DIV16, 5, 13, 2, 29,
+                                               BUS_MSTOP(11, BIT(3))),
+       DEF_MOD("rsci0_tclk",                   CLK_PLLCLN_DIV16, 5, 14, 2, 30,
+                                               BUS_MSTOP(11, BIT(3))),
+       DEF_MOD("rsci0_ps_ps3_n",               CLK_PLLCLN_DIV1024, 5, 15, 2, 31,
+                                               BUS_MSTOP(11, BIT(3))),
+       DEF_MOD("rsci0_ps_ps2_n",               CLK_PLLCLN_DIV256, 6, 0, 3, 0,
+                                               BUS_MSTOP(11, BIT(3))),
+       DEF_MOD("rsci0_ps_ps1_n",               CLK_PLLCLN_DIV64, 6, 1, 3, 1,
+                                               BUS_MSTOP(11, BIT(3))),
+       DEF_MOD("rsci1_pclk",                   CLK_PLLCLN_DIV16, 6, 2, 3, 2,
+                                               BUS_MSTOP(11, BIT(4))),
+       DEF_MOD("rsci1_tclk",                   CLK_PLLCLN_DIV16, 6, 3, 3, 3,
+                                               BUS_MSTOP(11, BIT(4))),
+       DEF_MOD("rsci1_ps_ps3_n",               CLK_PLLCLN_DIV1024, 6, 4, 3, 4,
+                                               BUS_MSTOP(11, BIT(4))),
+       DEF_MOD("rsci1_ps_ps2_n",               CLK_PLLCLN_DIV256, 6, 5, 3, 5,
+                                               BUS_MSTOP(11, BIT(4))),
+       DEF_MOD("rsci1_ps_ps1_n",               CLK_PLLCLN_DIV64, 6, 6, 3, 6,
+                                               BUS_MSTOP(11, BIT(4))),
+       DEF_MOD("rsci2_pclk",                   CLK_PLLCLN_DIV16, 6, 7, 3, 7,
+                                               BUS_MSTOP(11, BIT(5))),
+       DEF_MOD("rsci2_tclk",                   CLK_PLLCLN_DIV16, 6, 8, 3, 8,
+                                               BUS_MSTOP(11, BIT(5))),
+       DEF_MOD("rsci2_ps_ps3_n",               CLK_PLLCLN_DIV1024, 6, 9, 3, 9,
+                                               BUS_MSTOP(11, BIT(5))),
+       DEF_MOD("rsci2_ps_ps2_n",               CLK_PLLCLN_DIV256, 6, 10, 3, 10,
+                                               BUS_MSTOP(11, BIT(5))),
+       DEF_MOD("rsci2_ps_ps1_n",               CLK_PLLCLN_DIV64, 6, 11, 3, 11,
+                                               BUS_MSTOP(11, BIT(5))),
+       DEF_MOD("rsci3_pclk",                   CLK_PLLCLN_DIV16, 6, 12, 3, 12,
+                                               BUS_MSTOP(11, BIT(6))),
+       DEF_MOD("rsci3_tclk",                   CLK_PLLCLN_DIV16, 6, 13, 3, 13,
+                                               BUS_MSTOP(11, BIT(6))),
+       DEF_MOD("rsci3_ps_ps3_n",               CLK_PLLCLN_DIV1024, 6, 14, 3, 14,
+                                               BUS_MSTOP(11, BIT(6))),
+       DEF_MOD("rsci3_ps_ps2_n",               CLK_PLLCLN_DIV256, 6, 15, 3, 15,
+                                               BUS_MSTOP(11, BIT(6))),
+       DEF_MOD("rsci3_ps_ps1_n",               CLK_PLLCLN_DIV64, 7, 0, 3, 16,
+                                               BUS_MSTOP(11, BIT(6))),
+       DEF_MOD("rsci4_pclk",                   CLK_PLLCLN_DIV16, 7, 1, 3, 17,
+                                               BUS_MSTOP(11, BIT(7))),
+       DEF_MOD("rsci4_tclk",                   CLK_PLLCLN_DIV16, 7, 2, 3, 18,
+                                               BUS_MSTOP(11, BIT(7))),
+       DEF_MOD("rsci4_ps_ps3_n",               CLK_PLLCLN_DIV1024, 7, 3, 3, 19,
+                                               BUS_MSTOP(11, BIT(7))),
+       DEF_MOD("rsci4_ps_ps2_n",               CLK_PLLCLN_DIV256, 7, 4, 3, 20,
+                                               BUS_MSTOP(11, BIT(7))),
+       DEF_MOD("rsci4_ps_ps1_n",               CLK_PLLCLN_DIV64, 7, 5, 3, 21,
+                                               BUS_MSTOP(11, BIT(7))),
+       DEF_MOD("rsci5_pclk",                   CLK_PLLCLN_DIV16, 7, 6, 3, 22,
+                                               BUS_MSTOP(11, BIT(8))),
+       DEF_MOD("rsci5_tclk",                   CLK_PLLCLN_DIV16, 7, 7, 3, 23,
+                                               BUS_MSTOP(11, BIT(8))),
+       DEF_MOD("rsci5_ps_ps3_n",               CLK_PLLCLN_DIV1024, 7, 8, 3, 24,
+                                               BUS_MSTOP(11, BIT(8))),
+       DEF_MOD("rsci5_ps_ps2_n",               CLK_PLLCLN_DIV256, 7, 9, 3, 25,
+                                               BUS_MSTOP(11, BIT(8))),
+       DEF_MOD("rsci5_ps_ps1_n",               CLK_PLLCLN_DIV64, 7, 10, 3, 26,
+                                               BUS_MSTOP(11, BIT(8))),
+       DEF_MOD("rsci6_pclk",                   CLK_PLLCLN_DIV16, 7, 11, 3, 27,
+                                               BUS_MSTOP(11, BIT(9))),
+       DEF_MOD("rsci6_tclk",                   CLK_PLLCLN_DIV16, 7, 12, 3, 28,
+                                               BUS_MSTOP(11, BIT(9))),
+       DEF_MOD("rsci6_ps_ps3_n",               CLK_PLLCLN_DIV1024, 7, 13, 3, 29,
+                                               BUS_MSTOP(11, BIT(9))),
+       DEF_MOD("rsci6_ps_ps2_n",               CLK_PLLCLN_DIV256, 7, 14, 3, 30,
+                                               BUS_MSTOP(11, BIT(9))),
+       DEF_MOD("rsci6_ps_ps1_n",               CLK_PLLCLN_DIV64, 7, 15, 3, 31,
+                                               BUS_MSTOP(11, BIT(9))),
+       DEF_MOD("rsci7_pclk",                   CLK_PLLCLN_DIV16, 8, 0, 4, 0,
+                                               BUS_MSTOP(11, BIT(10))),
+       DEF_MOD("rsci7_tclk",                   CLK_PLLCLN_DIV16, 8, 1, 4, 1,
+                                               BUS_MSTOP(11, BIT(10))),
+       DEF_MOD("rsci7_ps_ps3_n",               CLK_PLLCLN_DIV1024, 8, 2, 4, 2,
+                                               BUS_MSTOP(11, BIT(10))),
+       DEF_MOD("rsci7_ps_ps2_n",               CLK_PLLCLN_DIV256, 8, 3, 4, 3,
+                                               BUS_MSTOP(11, BIT(10))),
+       DEF_MOD("rsci7_ps_ps1_n",               CLK_PLLCLN_DIV64, 8, 4, 4, 4,
+                                               BUS_MSTOP(11, BIT(10))),
+       DEF_MOD("rsci8_pclk",                   CLK_PLLCLN_DIV16, 8, 5, 4, 5,
+                                               BUS_MSTOP(11, BIT(11))),
+       DEF_MOD("rsci8_tclk",                   CLK_PLLCLN_DIV16, 8, 6, 4, 6,
+                                               BUS_MSTOP(11, BIT(11))),
+       DEF_MOD("rsci8_ps_ps3_n",               CLK_PLLCLN_DIV1024, 8, 7, 4, 7,
+                                               BUS_MSTOP(11, BIT(11))),
+       DEF_MOD("rsci8_ps_ps2_n",               CLK_PLLCLN_DIV256, 8, 8, 4, 8,
+                                               BUS_MSTOP(11, BIT(11))),
+       DEF_MOD("rsci8_ps_ps1_n",               CLK_PLLCLN_DIV64, 8, 9, 4, 9,
+                                               BUS_MSTOP(11, BIT(11))),
+       DEF_MOD("rsci9_pclk",                   CLK_PLLCLN_DIV16, 8, 10, 4, 10,
+                                               BUS_MSTOP(11, BIT(12))),
+       DEF_MOD("rsci9_tclk",                   CLK_PLLCLN_DIV16, 8, 11, 4, 11,
+                                               BUS_MSTOP(11, BIT(12))),
+       DEF_MOD("rsci9_ps_ps3_n",               CLK_PLLCLN_DIV1024, 8, 12, 4, 12,
+                                               BUS_MSTOP(11, BIT(12))),
+       DEF_MOD("rsci9_ps_ps2_n",               CLK_PLLCLN_DIV256, 8, 13, 4, 13,
+                                               BUS_MSTOP(11, BIT(12))),
+       DEF_MOD("rsci9_ps_ps1_n",               CLK_PLLCLN_DIV64, 8, 14, 4, 14,
+                                               BUS_MSTOP(11, BIT(12))),
        DEF_MOD("scif_0_clk_pck",               CLK_PLLCM33_DIV16, 8, 15, 4, 15,
                                                BUS_MSTOP(3, BIT(14))),
        DEF_MOD("i3c_0_pclkrw",                 CLK_PLLCLN_DIV16, 9, 0, 4, 16,
@@ -351,6 +457,26 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
        DEF_RST(7, 6, 3, 7),            /* WDT_1_RESET */
        DEF_RST(7, 7, 3, 8),            /* WDT_2_RESET */
        DEF_RST(7, 8, 3, 9),            /* WDT_3_RESET */
+       DEF_RST(8, 1, 3, 18),           /* RSCI0_PRESETN */
+       DEF_RST(8, 2, 3, 19),           /* RSCI0_TRESETN */
+       DEF_RST(8, 3, 3, 20),           /* RSCI1_PRESETN */
+       DEF_RST(8, 4, 3, 21),           /* RSCI1_TRESETN */
+       DEF_RST(8, 5, 3, 22),           /* RSCI2_PRESETN */
+       DEF_RST(8, 6, 3, 23),           /* RSCI2_TRESETN */
+       DEF_RST(8, 7, 3, 24),           /* RSCI3_PRESETN */
+       DEF_RST(8, 8, 3, 25),           /* RSCI3_TRESETN */
+       DEF_RST(8, 9, 3, 26),           /* RSCI4_PRESETN */
+       DEF_RST(8, 10, 3, 27),          /* RSCI4_TRESETN */
+       DEF_RST(8, 11, 3, 28),          /* RSCI5_PRESETN */
+       DEF_RST(8, 12, 3, 29),          /* RSCI5_TRESETN */
+       DEF_RST(8, 13, 3, 30),          /* RSCI6_PRESETN */
+       DEF_RST(8, 14, 3, 31),          /* RSCI6_TRESETN */
+       DEF_RST(8, 15, 4, 0),           /* RSCI7_PRESETN */
+       DEF_RST(9, 0, 4, 1),            /* RSCI7_TRESETN */
+       DEF_RST(9, 1, 4, 2),            /* RSCI8_PRESETN */
+       DEF_RST(9, 2, 4, 3),            /* RSCI8_TRESETN */
+       DEF_RST(9, 3, 4, 4),            /* RSCI9_PRESETN */
+       DEF_RST(9, 4, 4, 5),            /* RSCI9_TRESETN */
        DEF_RST(9, 5, 4, 6),            /* SCIF_0_RST_SYSTEM_N */
        DEF_RST(9, 6, 4, 7),            /* I3C_0_PRESETN */
        DEF_RST(9, 7, 4, 8),            /* I3C_0_TRESETN */