For (T3) "ADD (SP plus register)", allow "add rX, SP, rY, lsl

#{1,2,3}" as well as the non-shifted version.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2266

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index c51de011ce04e6b7a77b3faa8e36db40b013664b..5935b1e3b3a27a601f8d5558d68b8eca61839745 100644 (file)
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -16365,10 +16365,10 @@ DisResult disInstr_THUMB_WRK (
       UInt how  = INSN1(5,4);
 
       Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM);
-      /* but allow "add.w reg, sp, reg   w/ no shift
+      /* but allow "add.w reg, sp, reg, lsl #N for N=0,1,2 or 3
          (T3) "ADD (SP plus register) */
       if (!valid && INSN0(8,5) == BITS4(1,0,0,0) // add
-          && rD != 15 && rN == 13 && imm5 == 0 && how == 0) {
+          && rD != 15 && rN == 13 && imm5 <= 3 && how == 0) {
          valid = True;
       }
       /* also allow "sub.w reg, sp, reg   w/ no shift