arm64: tegra: Add Tegra264 GPIO controllers

Add device tree nodes for MAIN, AON and UPHY GPIO controller instances.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index 5214cec21204badec2de3f2f35bd97e96c7d2f9b..06d8357bdf527dd6b3bd5f5abd80751374fc0086 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3277,6 +3277,50 @@
                        status = "disabled";
                };
 
+               gpio_main: gpio@c300000 {
+                       compatible = "nvidia,tegra264-gpio";
+                       reg = <0x00 0x0c300000 0x0 0x4000>,
+                             <0x00 0x0c310000 0x0 0x4000>;
+                       reg-names = "security", "gpio";
+                       wakeup-parent = <&pmc>;
+                       interrupts =  <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
                serial@c4e0000 {
                        compatible = "nvidia,tegra264-utc";
                        reg = <0x0 0x0c4e0000 0x0 0x8000>,
@@ -3347,6 +3391,22 @@
                        #interrupt-cells = <2>;
                        interrupt-controller;
                };
+
+               gpio_aon: gpio@cf00000 {
+                       compatible = "nvidia,tegra264-gpio-aon";
+                       reg = <0x0 0x0cf00000 0x0 0x10000>,
+                             <0x0 0x0cf10000 0x0 0x1000>;
+                       reg-names = "security", "gpio";
+                       wakeup-parent = <&pmc>;
+                       interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
        };
 
        /* TOP_MMIO */
@@ -3802,6 +3862,34 @@
                         <0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 GiB) */
                         <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */
 
+               gpio_uphy: gpio@8300000 {
+                       compatible = "nvidia,tegra264-gpio-uphy";
+                       reg = <0x00 0x08300000 0x0 0x2000>,
+                             <0x00 0x08310000 0x0 0x2000>;
+                       reg-names = "security", "gpio";
+                       wakeup-parent = <&pmc>;
+                       interrupts = <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+               };
+
                pci@8400000 {
                        compatible = "nvidia,tegra264-pcie";
                        reg = <0xa8 0xb0000000 0x0 0x10000000>,