arm: [MVE intrinsics] factorize vqdmullbq vqdmulltq

Factorize vqdmullbq, vqdmulltq builtins so that they use the same
parameterized names.

2022-12-12  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (MVE_VQDMULLxQ, MVE_VQDMULLxQ_M)
	(MVE_VQDMULLxQ_M_N, MVE_VQDMULLxQ_N): New.
	(mve_insn): Add vqdmullb, vqdmullt.
	(supf): Add VQDMULLBQ_S, VQDMULLBQ_M_S, VQDMULLBQ_M_N_S,
	VQDMULLBQ_N_S, VQDMULLTQ_S, VQDMULLTQ_M_S, VQDMULLTQ_M_N_S,
	VQDMULLTQ_N_S.
	* config/arm/mve.md (mve_vqdmullbq_n_s<mode>)
	(mve_vqdmulltq_n_s<mode>): Merge into ...
	(@mve_<mve_insn>q_n_<supf><mode>): ... this.
	(mve_vqdmullbq_s<mode>, mve_vqdmulltq_s<mode>): Merge into ...
	(@mve_<mve_insn>q_<supf><mode>): ... this.
	(mve_vqdmullbq_m_n_s<mode>, mve_vqdmulltq_m_n_s<mode>): Merge into
	...
	(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
	(mve_vqdmullbq_m_s<mode>, mve_vqdmulltq_m_s<mode>): Merge into ...
	(@mve_<mve_insn>q_m_<supf><mode>): ... this.

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index abd904da11e362ba9daa26ed1c238814d38716b2..f88da604c19deb40387d99c137bbc70b08b0335f 100644 (file)
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -764,6 +764,26 @@
                     VMLSLDAVAXQ_P_S
                     ])
 
+(define_int_iterator MVE_VQDMULLxQ [
+                    VQDMULLBQ_S
+                    VQDMULLTQ_S
+                    ])
+
+(define_int_iterator MVE_VQDMULLxQ_M [
+                    VQDMULLBQ_M_S
+                    VQDMULLTQ_M_S
+                    ])
+
+(define_int_iterator MVE_VQDMULLxQ_M_N [
+                    VQDMULLBQ_M_N_S
+                    VQDMULLTQ_M_N_S
+                    ])
+
+(define_int_iterator MVE_VQDMULLxQ_N [
+                    VQDMULLBQ_N_S
+                    VQDMULLTQ_N_S
+                    ])
+
 (define_int_iterator MVE_VQxDMLxDHxQ_S [
                     VQDMLADHQ_S
                     VQDMLADHXQ_S
@@ -985,6 +1005,14 @@
                 (VQDMULHQ_M_S "vqdmulh")
                 (VQDMULHQ_N_S "vqdmulh")
                 (VQDMULHQ_S "vqdmulh")
+                (VQDMULLBQ_M_N_S "vqdmullb")
+                (VQDMULLBQ_M_S "vqdmullb")
+                (VQDMULLBQ_N_S "vqdmullb")
+                (VQDMULLBQ_S "vqdmullb")
+                (VQDMULLTQ_M_N_S "vqdmullt")
+                (VQDMULLTQ_M_S "vqdmullt")
+                (VQDMULLTQ_N_S "vqdmullt")
+                (VQDMULLTQ_S "vqdmullt")
                 (VQMOVNBQ_M_S "vqmovnb") (VQMOVNBQ_M_U "vqmovnb")
                 (VQMOVNBQ_S "vqmovnb") (VQMOVNBQ_U "vqmovnb")
                 (VQMOVNTQ_M_S "vqmovnt") (VQMOVNTQ_M_U "vqmovnt")
@@ -2425,6 +2453,14 @@
                       (VQDMLASHQ_N_S "s")
                       (VQRDMLAHQ_N_S "s")
                       (VQRDMLASHQ_N_S "s")
+                      (VQDMULLBQ_S "s")
+                      (VQDMULLBQ_M_S "s")
+                      (VQDMULLBQ_M_N_S "s")
+                      (VQDMULLBQ_N_S "s")
+                      (VQDMULLTQ_S "s")
+                      (VQDMULLTQ_M_S "s")
+                      (VQDMULLTQ_M_N_S "s")
+                      (VQDMULLTQ_N_S "s")
                       ])
 
 ;; Both kinds of return insn.

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 14634cbf3339015d29eb39cef9d411ea28fe974a..e75a30b7ed447bab43ca43f3fcf61137b876515b 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1503,62 +1503,34 @@
 ])
 
 ;;
-;; [vqdmullbq_n_s])
+;; [vqdmullbq_n_s]
+;; [vqdmulltq_n_s]
 ;;
-(define_insn "mve_vqdmullbq_n_s<mode>"
-  [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
-       (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
-                                 (match_operand:<V_elem> 2 "s_register_operand" "r")]
-        VQDMULLBQ_N_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vqdmullb.s%#<V_sz_elem>     %q0, %q1, %2"
-  [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vqdmullbq_s])
-;;
-(define_insn "mve_vqdmullbq_s<mode>"
-  [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
-       (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
-                                 (match_operand:MVE_5 2 "s_register_operand" "w")]
-        VQDMULLBQ_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vqdmullb.s%#<V_sz_elem>     %q0, %q1, %q2"
-  [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vqdmulltq_n_s])
-;;
-(define_insn "mve_vqdmulltq_n_s<mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
   [
    (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
                                  (match_operand:<V_elem> 2 "s_register_operand" "r")]
-        VQDMULLTQ_N_S))
+        MVE_VQDMULLxQ_N))
   ]
   "TARGET_HAVE_MVE"
-  "vqdmullt.s%#<V_sz_elem>     %q0, %q1, %2"
+  "<mve_insn>.s%#<V_sz_elem>\t%q0, %q1, %2"
   [(set_attr "type" "mve_move")
 ])
 
 ;;
-;; [vqdmulltq_s])
+;; [vqdmullbq_s]
+;; [vqdmulltq_s]
 ;;
-(define_insn "mve_vqdmulltq_s<mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
   [
    (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:MVE_5 1 "s_register_operand" "w")
                                  (match_operand:MVE_5 2 "s_register_operand" "w")]
-        VQDMULLTQ_S))
+        MVE_VQDMULLxQ))
   ]
   "TARGET_HAVE_MVE"
-  "vqdmullt.s%#<V_sz_elem>     %q0, %q1, %q2"
+  "<mve_insn>.s%#<V_sz_elem>\t%q0, %q1, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -3228,70 +3200,38 @@
    (set_attr "length""8")])
 
 ;;
-;; [vqdmullbq_m_n_s])
-;;
-(define_insn "mve_vqdmullbq_m_n_s<mode>"
-  [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
-       (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
-                      (match_operand:MVE_5 2 "s_register_operand" "w")
-                      (match_operand:<V_elem> 3 "s_register_operand" "r")
-                      (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-        VQDMULLBQ_M_N_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %3"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
-;;
-;; [vqdmullbq_m_s])
-;;
-(define_insn "mve_vqdmullbq_m_s<mode>"
-  [
-   (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
-       (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
-                      (match_operand:MVE_5 2 "s_register_operand" "w")
-                      (match_operand:MVE_5 3 "s_register_operand" "w")
-                      (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-        VQDMULLBQ_M_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vqdmullbt.s%#<V_sz_elem>\t%q0, %q2, %q3"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
-;;
-;; [vqdmulltq_m_n_s])
+;; [vqdmullbq_m_n_s]
+;; [vqdmulltq_m_n_s]
 ;;
-(define_insn "mve_vqdmulltq_m_n_s<mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
   [
    (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
                       (match_operand:MVE_5 2 "s_register_operand" "w")
                       (match_operand:<V_elem> 3 "s_register_operand" "r")
                       (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-        VQDMULLTQ_M_N_S))
+        MVE_VQDMULLxQ_M_N))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %3"
+  "vpst\;<mve_insn>t.s%#<V_sz_elem>\t%q0, %q2, %3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
 ;;
-;; [vqdmulltq_m_s])
+;; [vqdmullbq_m_s]
+;; [vqdmulltq_m_s]
 ;;
-(define_insn "mve_vqdmulltq_m_s<mode>"
+(define_insn "@mve_<mve_insn>q_m_<supf><mode>"
   [
    (set (match_operand:<V_double_width> 0 "s_register_operand" "<earlyclobber_32>")
        (unspec:<V_double_width> [(match_operand:<V_double_width> 1 "s_register_operand" "0")
                       (match_operand:MVE_5 2 "s_register_operand" "w")
                       (match_operand:MVE_5 3 "s_register_operand" "w")
                       (match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
-        VQDMULLTQ_M_S))
+        MVE_VQDMULLxQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vqdmulltt.s%#<V_sz_elem>\t%q0, %q2, %q3"
+  "vpst\;<mve_insn>t.s%#<V_sz_elem>\t%q0, %q2, %q3"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])