]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
wifi: iwlwifi: fix the access to CNVR TOP registers
authorEmmanuel Grumbach <emmanuel.grumbach@intel.com>
Mon, 11 May 2026 17:36:19 +0000 (20:36 +0300)
committerMiri Korenblit <miriam.rachel.korenblit@intel.com>
Tue, 26 May 2026 12:17:09 +0000 (15:17 +0300)
For Dr and Sc, we need to wait until the TOP is ready to gets its
registers read by the host.

Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Reviewed-by: Daniel Gabay <daniel.gabay@intel.com>
Link: https://patch.msgid.link/20260511203428.09778340db51.I28d678ad404bbf8068f139666d38e29be5aa063b@changeid
Signed-off-by: Miri Korenblit <miriam.rachel.korenblit@intel.com>
drivers/net/wireless/intel/iwlwifi/iwl-io.c
drivers/net/wireless/intel/iwlwifi/iwl-io.h
drivers/net/wireless/intel/iwlwifi/iwl-prph.h
drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c

index b1944584c69315fa9533240345fd4f1708a673ff..c4ccfffdf6af91b2695d7c8d95496f9de321e414 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2003-2014, 2018-2022, 2024-2025 Intel Corporation
+ * Copyright (C) 2003-2014, 2018-2022, 2024-2026 Intel Corporation
  * Copyright (C) 2015-2016 Intel Deutschland GmbH
  */
 #include <linux/device.h>
@@ -168,6 +168,22 @@ int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
        return -ETIMEDOUT;
 }
 
+int iwl_poll_umac_prph_bits_no_grab(struct iwl_trans *trans, u32 addr,
+                                   u32 bits, u32 mask, int timeout)
+{
+       int t = 0;
+
+       do {
+               if ((iwl_read_umac_prph_no_grab(trans, addr) & mask) ==
+                   (bits & mask))
+                       return 0;
+               udelay(IWL_POLL_INTERVAL);
+               t += IWL_POLL_INTERVAL;
+       } while (t < timeout);
+
+       return -ETIMEDOUT;
+}
+
 void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
 {
        if (iwl_trans_grab_nic_access(trans)) {
index 5bcec239ffc4ac93363075b6d38a98218289c5ba..d920a32fc173cad0eb5f3ad855c90c2aa33814e5 100644 (file)
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
- * Copyright (C) 2018-2021, 2025 Intel Corporation
+ * Copyright (C) 2018-2021, 2025-2026 Intel Corporation
  */
 #ifndef __iwl_io_h__
 #define __iwl_io_h__
@@ -51,6 +51,8 @@ static inline void iwl_write_prph(struct iwl_trans *trans, u32 ofs, u32 val)
 
 int iwl_poll_prph_bit(struct iwl_trans *trans, u32 addr,
                      u32 bits, u32 mask, int timeout);
+int iwl_poll_umac_prph_bits_no_grab(struct iwl_trans *trans, u32 addr,
+                                   u32 bits, u32 mask, int timeout);
 void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);
 void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
                            u32 bits, u32 mask);
index a7214ddcfaf56d1051ba997de6c11e7f3c42ce48..6ca1f51b69a1cd1cc859df1b9b429dee3a4fc1bd 100644 (file)
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 /*
- * Copyright (C) 2005-2014, 2018-2025 Intel Corporation
+ * Copyright (C) 2005-2014, 2018-2026 Intel Corporation
  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
  * Copyright (C) 2016 Intel Deutschland GmbH
  */
@@ -411,6 +411,11 @@ enum {
 #define HPM_SECONDARY_DEVICE_STATE      0xa03404
 #define WFPM_MAC_OTP_CFG7_ADDR         0xa03338
 #define WFPM_MAC_OTP_CFG7_DATA         0xa0333c
+#define WFPM_RSRCS_4PHS_REQ_STTS       0xa033f8
+#define WFPM_RSRCS_4PHS_ACK_STTS       0xa033fc
+
+#define RSRC_REQ_CNVR_TOP BIT(6)
+#define RSRC_ACK_CNVR_TOP BIT(6)
 
 
 /* For UMAG_GEN_HW_STATUS reg check */
index a05f60f9224b484829d766d7bd2e1e418c03e2f0..377b2e30b540c191547772f726e548e4aa55ff1a 100644 (file)
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
 /*
- * Copyright (C) 2007-2015, 2018-2024 Intel Corporation
+ * Copyright (C) 2007-2015, 2018-2024, 2026 Intel Corporation
  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
  * Copyright (C) 2016-2017 Intel Deutschland GmbH
  */
@@ -4000,6 +4000,30 @@ static void get_crf_id(struct iwl_trans *iwl_trans,
        else
                sd_reg_ver_addr = SD_REG_VER;
 
+       /* wait until the device is ready to access the prph registers */
+       if (iwl_trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_DR ||
+           iwl_trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_SC) {
+               u32 req = iwl_read_umac_prph_no_grab(iwl_trans,
+                                                    WFPM_RSRCS_4PHS_REQ_STTS);
+               int ret;
+
+               if (!(req & RSRC_REQ_CNVR_TOP)) {
+                       IWL_ERR(iwl_trans,
+                               "WFPM_RSRCS_4PHS_REQ_STTS bit 6 is clear 0x%x\n",
+                               req);
+                       return;
+               }
+
+               ret = iwl_poll_umac_prph_bits_no_grab(iwl_trans,
+                                                     WFPM_RSRCS_4PHS_ACK_STTS,
+                                                     RSRC_ACK_CNVR_TOP,
+                                                     RSRC_ACK_CNVR_TOP,
+                                                     50 * 1000);
+               if (ret < 0)
+                       IWL_ERR(iwl_trans,
+                               "WFPM_RSRCS_4PHS_ACK_STTS bit 6 is clear\n");
+       }
+
        /* Enable access to peripheral registers */
        val = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG);
        val |= WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK;